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ASML, TSMC and imec present 300mm integration route for industry-ready 2D-material-based transistors

28 d ago

ASML, TSMC, and imec have jointly presented a robust 300mm integration route for 2D-material-based nFETs and pFETs at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits in Honolulu, Hawaii (14–18 June). For the first time, scaled nFETs using MoS2 and pFETs using WS2 or WSe2 as channel materials achieved a 50nm contacted poly pitch (CPP) with good current–voltage characteristics, representing a crucial step toward industrial adoption of 2D-material-based transistors for ultra-scaled logic and back-end/wafer backside applications. Transition-metal dichalcogenides (TMDs) like MoS2, WS2, and WSe2 offer atomically thin channels with excellent electrostatic control and acceptable mobilities at ultra-scaled dimensions, but lacked a scalable 300mm integration process. The collaboration delivered three key outcomes: (1) world-first scaled nFETs and pFETs with 50nm CPP; (2) very low off-current (Ioff) at zero gate voltage (Vg=0V) for both polarities; and (3) pFETs with WSe2 performing close to record lab devices. With 94% operational transistors (Imax/Imin >105), the CMOS-like integration on a 300mm wafer proved robust and stable. The process flow is also applicable to other 2D channel materials. Key to achieving scaled CPP was single-patterning EUV lithography, optimized with ASML. An innovative “reverse” thin-film transistor (TFT) flow—using bottom contacts with an overlapping deposited gate, where TMD channels are transferred onto pre-patterned tungsten trenches—accounts for the ideal off-current behavior. TSMC’s VP & CTO Dr. Min Cao emphasized de-risking the lab-to-fab transition, while ASML’s Etienne De Poortere noted that EUV lithography enabled channel lengths as small as 28nm at advanced nodes. imec’s Gouri Sankar Kar invited further ecosystem collaborations to drive performance for this new class of channel materials and devices.