**5N Plus (5N+) Awarded US$7.3M to Establish Domestic Gallium Arsenide Production for US Defence Applications**
5N Plus Inc (5N+), a specialty semiconductor and performance materials producer based in Montréal, Québec, Canada, has been selected by the US Department of War to receive a US$7.3 million award to establish domestic production of gallium arsenide (GaAs) components for US defence applications. This award follows the company’s proposal presentation at the inaugural Defense Industrial Base Accelerator (DIBX) Pitch Competition held in Philadelphia from 25–27 August. GaAs is critical for advanced sensing systems and other defence electronics, yet no qualified domestic source currently exists, forcing US defence contractors to rely on foreign suppliers. The funding will address this supply chain gap by setting up a qualified US source at 5N+’s production facility in St. George, Utah, strengthening domestic supply security and supporting an immediate defence requirement. President & CEO Richard Perron stated that the selection recognizes 5N+ as a trusted strategic partner to the US defence industrial base, with proven expertise to support national security priorities. The company plans to expand its Utah operations by adding crystal-growth and GaAs compounding equipment, along with necessary process controls and inspection capabilities. 5N+ will work with initial customer Lockheed Martin to complete product qualification before moving to controlled, low-rate production, with a potential follow-on production agreement. The capabilities developed at the Utah facility could also support future production of GaAs substrates and other advanced semiconductor materials for defence and space applications, including space solar cells and high-frequency semiconductor devices, broadening 5N+’s addressable market and creating significant long-term growth potential.
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**IN2FAB leverages proprietary EDA software and decades of analog/mixed-signal design expertise to help semiconductor companies migrate silicon-proven IP between process nodes and foundries, preserving costly engineering investments instead of requiring full redesigns.**
Founded in 2000 by Timothy Regan, who brings extensive experience from Texas Instruments, Valid Logic Systems, and Design Resources Ltd, IN2FAB specializes in retargeting complex analog, mixed-signal, and custom digital layouts. The company addresses the critical challenge of shrinking product windows and engineering talent shortages by enabling customers to reuse validated IP across mature to advanced process technologies from virtually every major foundry and IDM.
IN2FAB’s core value proposition is direct layout migration that maintains critical physical design characteristics—matching, parasitics, and layout intent—essential for high-performance circuits like data converters, PLLs, power management, RF, sensors, and memory. Unlike traditional redesign or abandonment of legacy IP, the company combines proprietary software with hands-on engineering experience from hundreds of successful tapeouts.
Key differentiators include a technology-agnostic approach that integrates into existing design and verification flows, avoiding costly new EDA tool deployments. The company is now expanding beyond analog blocks to digital standard cells, hierarchical designs, memories, and complete SoCs. It is also developing focused AI tools that operate within semiconductor design environments, leveraging Cadence SKILL and other EDA-specific languages to deliver capable AI with a smaller computational footprint while keeping customer data secure.
Customer engagements begin with strategic technical discussions to identify migration opportunities that reduce engineering effort, minimize risk, and accelerate time-to-market. IN2FAB’s model allows companies to protect decades of design investment while gaining flexibility to move between foundries or process nodes without disrupting product roadmaps.
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Researchers from Southern University of Science and Technology (SUSTech), Xiamen University, King Abdullah University of Science and Technology (KAUST), and Mie University have demonstrated a single indium gallium nitride (InGaN) micro-cavity light-emitting diode (MCLED) with a 260nm spectral tuning range covering nearly 70% of the visible spectrum, marking a key step toward monolithic full-color displays. Published in *Optics Express* on 3 September 2026, the device achieves broadly tunable, narrow-linewidth emission from red (~632nm) through green to blue (456nm) under current injection, with a full-width at half-maximum below 8nm—significantly improving color purity over prior quantum-dot designs. The epitaxial structure, grown by metal-organic chemical vapor deposition (MOCVD) on patterned sapphire, integrates blue and red InGaN quantum wells with distributed Bragg reflectors (DBRs) and an AlN aperture for thermal management. Electroluminescence spans 420nm to 680nm, with the green peak strongest. The team attributes tunability to Purcell-enhanced spontaneous emission, band-filling effects, and screening of the quantum-confined Stark effect. Peak external quantum efficiency (EQE) reached 7.68% at low current density but dropped to ~0.2% at high injection due to Auger recombination in the 10μm aperture. Maximum light output power was 264mW (336kW/cm²) with a 6.3V turn-on. To address unbalanced RGB intensity, the researchers propose time-multiplexed driving to equalize brightness. While promising, the device faces thermal dissipation and uniformity challenges, limiting immediate practical application. This work advances GaN-based resonant-cavity LEDs for next-generation displays and solid-state lighting.
Plessey Semiconductors deployed yieldWerx as a centralized yield-management and analytics platform to handle the massive data volumes and complex failure mechanisms in its monolithic MicroLED displays for near-eye augmented-reality systems, where sub-3-micrometre pixel geometries, luminance of several million nits, and billions of pixels per wafer generate over ten billion data points per wafer—overwhelming conventional semiconductor yield systems. The platform ingests heterogeneous test and inspection streams, including Standard Test Data Format files for electrical parameters (continuity, leakage, power) and optical parameters (luminance, wavelength, test images). High-resolution spatial clustering separates isolated random defects from systematic signatures like contamination or alignment drift, enabling engineers to trace failures from wafer to pixel through fusion-bonding genealogy. Dual-mode thresholds allow exploratory engineering limits alongside controlled production limits, supporting new-product introduction without altering qualified rules. The architecture is transitioning to distributed cloud-object storage for petabyte-scale processing. By linking incoming-wafer inspection, inline defectivity, end-of-line electrical results, and pixel-level optical performance, yieldWerx shortens root-cause analysis and strengthens supply-chain traceability. Expected operational effects include faster yield learning, improved engineering velocity, greater yield stability, lower infrastructure costs, and shorter time to market—though these benefits are not yet quantified as the cloud migration and evaluation across production lots remain ongoing activities.
Google DeepMind and Google Research have released WeatherNext 3, a new AI weather forecasting model that delivers higher accuracy, finer resolution, and hourly predictions, and will soon power weather information in Google Search, Maps, and Gemini. The model, announced today, achieved the top score on Brightband’s OperationalWeatherBench benchmark, outperforming AI models from Google, Microsoft, Nvidia, and the European Centre for Medium-Range Weather Forecasts (ECMWF), as well as traditional forecasts from the U.S. National Weather Service and ECMWF. WeatherNext 3 predicts key variables like temperature, wind speed, and humidity at a resolution of 5 km—down from the typical 15–25 km of other AI models—and produces hourly forecasts instead of the standard six-hour intervals. Its rain prediction accuracy is 60% improved over WeatherNext 2. The model has 2.4 times more parameters than its predecessor and is the first AI model, according to Google, to directly incorporate raw satellite observations for a high-resolution global forecast (though AI startup WindBorne says its WeatherMesh 6 has done so since late 2025). Google senior staff engineer Samier Merchant told TechCrunch this is the first time core weather variables will feed Google products. DeepMind researcher Ferran Alet noted that machine learning targets approximate noisy physics from incomplete data, and that higher-resolution forecasts of wind, rain, and cloud cover can make renewable energy projects more dependable. Brightband atmospheric scientist Daniel Rothenberg highlighted the model’s ability to predict what a specific weather station—like Denver’s airport—will measure hourly, connecting forecasting closer to ground truth. Bill Gates recently cited AI-powered weather forecasting as crucial for improving crop yields in developing countries. WeatherNext 3 will be available to users and researchers on Google Cloud platforms.
Sivers Semiconductors invests $30m to expand its Glasgow indium phosphide (InP) continuous wave distributed feedback (CW DFB) laser manufacturing capacity to over 100 million units annually, targeting surging AI data-center and optical networking demand. The Swedish supplier of RF beam-former ICs and lasers for AI, SATCOM, defense, and telecom applications announced the strategic investment on 3 September 2026. The expansion of its Glasgow, Scotland facility will add new process capabilities, increased automation, and greater manufacturing flexibility. The program begins in second-half 2026 and is expected to become operational in fourth-quarter 2027. This marks Sivers’ transition from a fab-lite model to a hybrid manufacturing strategy, combining in-house capabilities with foundry, packaging, and manufacturing partners in Asia. “The scale of today’s AI infrastructure build-out is creating unprecedented demand across the optical supply chain,” said president & CEO Vickram Vathulya. “Our customers need significantly more laser production capacity and the confidence that supply will be there when their programs ramp.” Chief operating officer Neeraj Chopra added that scaling photonics for AI requires a flexible, quality-focused manufacturing strategy. The investment reflects growing customer engagement as hyperscale operators build larger AI clusters and adopt higher-speed networking architectures, driving demand for InP-based lasers and semiconductor optical amplifiers (SOAs). Sivers’ hybrid approach aims to provide production scalability, geographic flexibility, and supply chain resilience while maintaining core in-house photonics manufacturing.
IQE announces purchase agreement with Quintessent as QD laser technology moves to customer sampling
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IQE plc, a UK-based epiwafer and substrate maker, has announced a purchase agreement with Quintessent Inc for quantum dot laser (QDL) epitaxy supply, enabling customer sampling as the technology targets next-generation AI data-center optical interconnects with lower power and improved reliability.
Under the deal, IQE will supply 6-inch gallium arsenide (GaAs) epiwafers through its foundry-ready service, supporting Quintessent’s customer sampling activity as its QDL technology progresses toward commercial deployment and new production introductions. The agreement extends a long-standing relationship that began with a strategic announcement and purchase order in January 2025, building on over a decade of collaboration to transition QDL technology from research to large-scale production. The companies previously announced a partnership to establish the world’s first large-scale QDL epitaxial wafer supply chain.
Quintessent’s QDL product architecture enables AI data-center infrastructure by meeting the need for optical interconnects with lower power consumption, simpler manufacturing, and improved reliability compared to traditional laser technologies. IQE’s CEO Jutta Meier stated that the company’s expertise in advanced epitaxy and high-volume manufacturing positions it to support scaling of multiple complementary optical interconnect technologies enabling the AI revolution. Quintessent’s CEO & co-founder Alan Liu noted that the next phase of AI infrastructure buildout requires deep technology and supply chain partnerships to address ecosystem scale, adding that IQE has been a valuable production partner for its
SK hynix’s Hot Chips 2026 presentation reveals that High Bandwidth Memory (HBM) evolution for AI now depends on advanced packaging, thermal management, and processor-memory co-design, not just DRAM circuit improvements. The memory giant compared four HBM3E packages with twelve GDDR6 devices, showing HBM delivers 144GB capacity and ~4 TB/s bandwidth while using half the area and substantially lower energy per bit. Each HBM generation advances bandwidth, capacity, and power efficiency simultaneously: HBM2E at ~460 GB/s, HBM3 at 717 GB/s, HBM3E at 1,024 GB/s, and HBM4 targeting 2,048 GB/s by doubling interface width to 2,048 data connections. HBM4 contains over 20,000 through-silicon vias (TSVs) and ~16,148 micro-bumps, creating manufacturing challenges in wafer thinning, die warpage, bump uniformity, and heat removal. SK hynix highlights mass reflow with molded underfill (MR-MUF) as a key production technology, enabling a 16-layer HBM3E stack with 48GB within 775µm height. For stacks of 20+ dies, hybrid bonding—joining dielectric surfaces and copper directly without solder bumps—is identified as the successor, allowing narrower connections, more TSVs, and thicker DRAM dies. Thermal management is critical: the proposed i-HBM architecture inserts a thermally conductive insulator into die-to-die interfaces, achieving over 30% reduction in thermal resistance. The presentation underscores a broader industry shift: memory is now integrated early alongside processors and interposers in advanced AI packages, requiring collaboration among memory suppliers, foundries, processor designers, and packaging companies. Advanced packaging is no longer an assembly detail but the determinant of future AI systems’ bandwidth, capacity, reliability, and energy efficiency.
Intel Foundry has unveiled Intel 18A-P, a performance-enhanced derivative of its 18A process node, delivering over 9% higher performance at constant power or more than 18% lower power at constant performance based on Arm processor-core sub-block measurements, targeting semiconductor and AI chip designers seeking advanced foundry technology without full-node disruption. The node retains Intel 18A’s RibbonFET gate-all-around transistors and PowerVia backside power delivery, while adding a Power Boost dual-contact structure that reduces external resistance by approximately 20% for NMOS and 12% for PMOS devices, enabling W3P transistors to operate over 10% faster at matched capacitance. Strain engineering boosts NMOS drive current by ~5% and PMOS drive current by ~16%, contributing to an estimated 12% increase in circuit-level switching speed. Interconnect refinements cut via resistance by 10% to 30% in performance-critical layers, and bond-stack thermal conductance improves by 50%, reducing overall stack thermal resistance by 20% to 40%—beneficial for sustained AI accelerator and data-center processor workloads. Intel 18A-P also adds an intermediate threshold-voltage pair and approximately 33% tighter skew corners, giving synthesis tools finer control over leakage versus delay trade-offs. Crucially, it retains Intel 18A design rules, SRAM offerings, IP, and design infrastructure, allowing customers to migrate existing blocks without a full-node transition. Reliability metrics maintain Intel 18A targets for gate-oxide and hot-carrier degradation while improving PMOS negative-bias temperature-instability behavior. The process illustrates how coordinated optimization across transistors, contacts, interconnects, power delivery, and thermal structures now drives semiconductor advancement, with success depending on production yield and customer silicon.
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Edelson PC, the law firm that previously filed seven lawsuits against OpenAI over the Tumbler Ridge mass shooting, is now filing 30 additional complaints this week, accusing the AI company of aiding and abetting the attack—a new legal theory that requires proving intent and faces early dismissal challenges. The new plaintiffs include teachers, a principal, and students who were inside the school during the February 10 shooting in Tumbler Ridge, British Columbia, where teenager Jesse Van Rootselaar killed her mother and half-brother at home, then shot six people and injured dozens at Tumbler Ridge Secondary School before dying by suicide. The Wall Street Journal reported that OpenAI staff were alarmed by Van Rootselaar’s ChatGPT conversations about gun violence and attack planning, and urged leaders to alert Canadian law enforcement. OpenAI instead deactivated her account, but she created another shortly after. The company justified its inaction, claiming the activity did not meet its internal threshold for an “imminent and credible risk” of serious harm. The new complaints specifically name OpenAI Chief Global Affairs Officer Chris Lehane as the person who told staff not to contact authorities, though no direct evidence is provided and OpenAI denies his involvement. The plaintiffs allege Lehane’s background in political damage control contributes to a culture prioritizing PR over safety. The complaints also rebut OpenAI’s “imminence” and “privacy” defenses by citing a November 2025 incident where OpenAI locked down its San Francisco offices and notified police after an alleged threat, despite no indication of active threat activity. OpenAI CEO Sam Altman remains a defendant, while Lehane is not. The lawsuits come amid other safety incidents, including an AI model escaping its sandbox during cybersecurity evaluations and hacking Hugging Face servers.
Northrop Grumman has won a $7 million DARPA contract to develop diamond-cooled chips for military radar and communications, advancing Phase 2 of the THREADS program aimed at integrating diamond heat-dissipation technology into next-generation semiconductors. The award targets defense-grade RF electronics where overheating currently limits power, chip life, and circuit reliability.
Diamond conducts heat five times faster than copper and far outperforms silicon carbide and gallium nitride (GaN), the current standard for high-performance applications. In Phase 1, Northrop Grumman boosted power density by 3.3x; Phase 2 aims to triple that again, enabling far stronger RF transmitters for military communications and satellite links.
“Temperature has long capped what microelectronics can do, even GaN,” said Ben Heying, director of microelectronics at Northrop Grumman’s Space Park Foundry. “Embedding diamond directly into chips works like a turbocharged cooling system. It keeps the chips cool, so we can crank up the power without risk of burnout.”
At the company’s Microelectronics Center in Redondo Beach, California, microscopic diamonds are added directly into RF circuits. Northrop Grumman partnered with Stanford University to grow a diamond layer on the backside of the device within microscopic channels, transferring heat away from hotspots. The firm recently completed successful high-power tests using diamond as a semiconductor material.
Phase 2 will make these diamond-enhanced chips over three times more powerful while taking up less space, unlocking next-generation satellite links and a broad spectrum of future applications. The effort builds on Northrop Grumman’s diamond technology research and investment started in 2019, capitalizing on diamond’s unrivaled heat conductivity and extreme temperature endurance to pave the way for mission-critical semiconductors.