The NXP i.MX 95-based industrial HMI gives OEMs and system integrators a ready-to-use platform for modernizing their machine interfaces, adding local intelligence and scaling deployments. Modular Vision 10.1 MX95 is readily available through DigiKey. SECO, a high-tech company delivering integrated edge AI infrastructure and physical AI systems, today announces that its Modular Vision 10.1 MX95 has moved from the early-access pre-order phase to mass-production availability. Designed for OEMs and system integrators developing or modernizing industrial human-machine interfaces, the NXP i.MX 95-based platform combines computing, display, industrial connectivity and software in a ready-to-integrate solution, helping simplify the path from validation to deployment and subsequent scaling. The platform is also available through DigiKey, giving customers convenient access to individual or smaller quantities for limited-volume requirements, integration, validation and initial deployments. Simplifying industrial HMI integration Developing or refreshing an industrial HMI often requires OEMs and system integrators to bring together multiple elements, from computing and display technology to industrial connectivity and the software environment needed to operate and maintain the device over time. This can add integration effort and complexity, particularly when companies are updating established machine architectures or preparing new connected products. For these projects, Modular Vision 10.1 MX95 provides a practical path to introduce newer processing, connectivity and local intelligence capabilities into the next generation of industrial interfaces. Its integrated architecture is designed to support both new developments and the modernization of existing HMI designs, helping manufacturers evolve their products without having to approach each technology layer as a separate integration project. What Modular Vision 10.1 MX95 is ideal for Modular Vision 10.1 MX95 is suited to industrial applications where operators need immediate access to machine information and where local processing can add intelligence directly at the point of operation. In machine interfaces and monitoring systems, it can combine user interaction with the visualization of operating data and equipment status, supporting more responsive and information-rich HMIs. The platform is also well suited to quality inspection and other Edge AI applications that benefit from real-time analysis at the edge, as well as plant and equipment management scenarios where diagnostics, operational status and machine information need to be available directly on the shop floor. These capabilities make it relevant both for new intelligent HMI projects and for manufacturers looking to evolve existing product generations with more advanced compute and AI capabilities. Integrated hardware and software for easier deployment Built around the NXP i.MX 95 applications processor, Modular Vision 10.1 MX95 combines a 10.1-inch touch display with ≥400 nits brightness and a backlight lifetime of ≥30,000 hours, integrated graphics and AI acceleration of up to 2.0 TOPS/8 eTOPS, alongside the connectivity required for industrial HMI applications. Designed for panel-mount installations, the platform features front-side IP65 protection, integrated thermal management and a wide DC input range, supporting continuous operation across industrial environments. The platform also integrates hardware-based security capabilities supporting FIPS 140-3 compliance, strengthening its suitability for connected industrial deployments. Together, these capabilities provide OEMs with a consolidated platform for applications that require visualization, local processing and intelligent functions at the edge. Clea OS, SECO’s Yocto-based industrial operating system, provides the software foundation for the platform, extending the value of the hardware with capabilities designed to support security, software updates and device manageability over time. Together, this hardware-software approach helps OEMs address deployment and lifecycle management as part of the same system architecture, rather than as separate integration layers. As cybersecurity and lifecycle requirements become increasingly important under regulations such as the Cyber Resilience Act (CRA), this integrated approach helps OEMs reduce compliance complexity while supporting the development of secure, connected industrial devices. “For OEMs, the value of an advanced HMI platform lies not only in its technology, but in how effectively that technology can be turned into products that are ready for real-world deployment,” said Lorenzo Veltroni, Chief Product and Marketing Officer at SECO. “With Modular Vision 10.1 MX95, we are giving customers a consistent foundation to evolve their HMI applications with high-performance graphics, AI acceleration and secure connectivity, while simplifying integration and long-term product development.” SECO SECO (IOT.MI) is a high-tech company delivering integrated edge AI infrastructure and physical AI systems that bring intelligence directly into industrial devices. By combining advanced, modular hardware with Clea, its proprietary agentic Edge AI framework, SECO enables companies to deploy AI at the edge, turning field data into actionable insights and unlocking new services at the point of operation. SECO’s complete infrastructure helps customers accelerate AI adoption at industrial scale, enabling them to launch smarter products and capture innovative revenue streams and business models, while providing industrial-grade manufacturing and long-term support. With a global customer base spanning across industrial automation, robotics, medical, defense, transportation, energy, and vending, SECO is a trusted enabler of next-generation intelligent systems. SECO provides the US and Canada with comprehensive engineering, technical support, and business services from its headquarters in Rockville, Maryland, United States.
Affordable battlefield modernization at mission speed: New MOSA-compliant Expansion™ modules transform virtually any compatible platform into a rapidly upgradeable C5ISR and mission system, enabling low-cost insertion of plug-and-play AI, autonomy, advanced networking, secure storage, and next-generation warfighting capabilities without costly platform replacements. General Micro Systems (GMS), the undisputed leader in ultra-rugged small form factor (SFF) embedded computing for defense and aerospace applications, today unveiled its MOSA-compliant smart peripheral Expansion™ modules, a breakthrough family of Thunderbolt™-enabled subsystems that fundamentally redefine how advanced capabilities are deployed at the tactical edge. The company directly compares the MOSA modules’ affordability, scalability, and low design-in barrier with the older, more complex OpenVPX systems touted by the modern defense department. The secret ingredient is the open Thunderbolt interface. By combining Thunderbolt’s extraordinary high-speed connectivity and power delivery with GMS’s unmatched rugged computing expertise, these plug-and-play, open standard, compact, mission-ready modules enable defense and aerospace platforms to rapidly integrate powerful new capabilities with unprecedented simplicity for a fraction of the cost of a new system. Whether deployed in next-generation systems or connected to compatible fielded platforms, GMS Expansion modules deliver a faster, smarter, and dramatically more cost-effective path to modernization. As defense programs race to field artificial intelligence or super intelligence, autonomous mission systems, advanced sensors, and increasingly data-intensive technologies, conventional modernization strategies have become a major obstacle to innovation. Integrating new capabilities into existing platforms often demands costly hardware redesigns, lengthy integration cycles, and exhaustive testing and requalification efforts that can delay deployment for months or even years. GMS Expansion modules shatter this paradigm, providing a revolutionary COTS plug-and-play approach that dramatically accelerates technology insertion, reduces program risk, and enables warfighters to capitalize on breakthrough capabilities without the burden of extensive platform redesign or disruption. “Thunderbolt changed everything with its extraordinary ability to extend high-speed PCI Express connectivity, video, data, and power beyond the host computer,” said Ben Sharfi, CEO and Chief Architect of GMS. “The real breakthrough, however, is what GMS has engineered around it. We’ve harnessed Thunderbolt in ways conventional rugged computing architectures can’t match, enabling military platforms to gain advanced AI, super intelligence, autonomous mission systems, secure data movement, advanced networking, and mission-specific I/O without tearing apart the host system. What once required years of engineering, integration, and testing can be accomplished in a fraction of the time via a single open standard cable. Without Thunderbolt, this kind of expansion simply wouldn’t be possible, and without GMS’s unique engineering, it wouldn’t be possible in this extremely small form factor. It’s truly the most significant advancement in military platform modernization in decades.” GMS Expands Thunderbolt Capabilities for the Battlefield By extending high-speed PCI Express connectivity beyond the host computer, Thunderbolt allows compatible remote peripherals to communicate with the processing system through a high-bandwidth connection. Thunderbolt also supports DisplayPort video, USB connectivity, and in supported configurations, power delivery over a single cable, reducing cabling complexity while providing greater flexibility in where capabilities are installed. GMS takes these capabilities beyond conventional commercial applications, combining Thunderbolt 3/4/5 connectivity with proprietary ultra-rugged system engineering and complementary open interfaces, including USB 3/4 and high-speed Ethernet. The result is a family of compact, field-deployable subsystems designed to bring advanced computing, networking, storage, and mission-specific functionality beyond the physical boundaries of the host computer—without requiring extensive modifications to the underlying platform. Add Mission Capabilities Without Redesigning the Platform The Expansion modules deliver plug-and-play AI and autonomous mission system processing, high-performance computing, enterprise-class Ethernet switching, modular I/O, removable storage, conditioned power, advanced thermal management, and multi-domain security in compact, lightweight, ultra-rugged packages engineered for the harshest operational environments. Each module delivers mission-critical capabilities as independent, field-deployable subsystems that can be added whenever new requirements emerge, including: Artificial Intelligence, Autonomy & Vision Processing: The AI GPU Module, powered by NVIDIA® Jetson™ AGX Orin, instantly transforms virtually any military platform into an AI-enabled edge computing node. Supporting Camera Link, HD-SDI, CoaXPress™, 10GigE and other sensor interfaces. It delivers real-time AI inference, autonomous target recognition, sensor fusion, video analytics, autonomous mission system processing, and up to 100GigE networking output. The module provides one of the fastest available paths for bringing next-generation AI-enabled and autonomous mission capabilities to both legacy and newly developed systems. Workstation I/O (WSIO) Docking Station with Add-in I/O: Plug-and-play MOSA subsystem allows up to twelve (12) sites for add-in modules such as MIL-STD-1553, ARINC-429, CANbus, serial, SDR, A/D or D/A, resolver, Ethernet, GPS, 5G/LTE—or any I/O type on Mini-PCIe, M.2, or other miniature open standard interface. Built-in features include removable drive, 10GigE, DisplayPort video, and USB 3.x. WSIO is powered over Thunderbolt with single-cable connection between module and host computer. WSIO is the easiest and most affordable way to add massive capability and forward tech refresh to any system without modifying or requalifying the existing system. High-Speed Removable Mission Storage: Powered via the Thunderbolt data cable, the Storage Canister Module provides up to 64TB of secure, removable storage using sealed quad-U.2 or octal-M.2 architectures built for extreme military environments. Designed for ISR, SIGINT, EW, and mission-recording applications, the module supports rapid mission-data extraction, streamlined declassification workflows, and transfer rates up to 40Gbps, enabling operators to move mission-critical data from platform to exploitation systems in minutes. Cross-Domain Security & Encryption: The Expansion family includes dedicated hardware modules for secure multi-domain architectures, including the Encryption Module with integrated General Dynamics KG-175N, plus Red, Black, and LZ Domain I/O Controller Modules featuring TACDS® support, PTT, CAC readers, and FIPS 140-2 validated removable storage. Together, these modules simplify deployment of secure cross-domain systems while protecting sensitive mission data across multiple security enclaves and communications networks. Select cross domain modules are powered via the Thunderbolt cable. Networking, Routing & Modular I/O: The Intelligent Switch Module combines four 100GigE fiber ports and eight 10GigE copper ports to deliver high-bandwidth Layer 2/3 packet routing at the tactical edge. Complementing it, the Workstation I/O Module enables seamless integration of virtually any legacy or modern interface, including MIL-STD-1553, ARINC, CANbus, serial, digital, or analog I/O, without host redesign, software disruption, or platform requalification. Power Conditioning & Thermal Management: Expansion modules also address two of the most persistent deployment challenges: power and cooling. Available options include 2kW MIL-STD-1275-compliant AC/DC power supplies, integrated UPS modules utilizing supercapacitor or lithium-ion technology, and advanced active or passive cooling modules leveraging vapor-phase thermal management to maintain maximum performance across the most extreme operating environments. Power modules offer Thunderbolt Power Delivery, sufficient to power multiple Expansion modules. “Defense programs can’t afford to spend years re-engineering platforms every time a new AI capability, autonomous mission requirement, sensor suite, or security standard emerges,” Sharfi added. “Expansion gives program managers a faster, more flexible way to field advanced capabilities while preserving existing platform investments. That means accelerating technology insertion, reducing integration risk, and getting critical capabilities into the hands of warfighters when they’re needed—not years later. I mean, if you had to do the same thing with OpenVPX—itself a 20-year-old technology—it would be at 8-10x the cost and over 10x the weight of Expansion modules. And that’s not to mention the development time of years.” As military organizations increasingly prioritize autonomous systems, AI-enabled operations, open architectures, and rapid technology insertion, the Expansion family provides a practical bridge between today’s deployed platforms and tomorrow’s mission requirements. By decoupling capability growth from platform redesign, GMS enables defense organizations to modernize at the pace of technology rather than the pace of traditional acquisition. The result is a dramatically faster path to fielding AI-enabled and autonomous mission systems across the force while preserving existing platform investments. About General Micro Systems For nearly 50 years, General Micro Systems (GMS) has pioneered the industry’s most advanced high-density, compute-intensive, modular, and rugged embedded computing systems. Designed and manufactured in the United States, GMS solutions power mission-critical applications across defense, aerospace, int
Byline: Richard Shreiner Modern semiconductor architectures are pushing the absolute limits of physical scaling. As data rates climb into sub-picosecond regimes across high-performance computing, 5G/6G infrastructure, and advanced AI clusters, physical layer (Layer 1) signal integrity has shifted from an engineering challenge to a critical bottleneck. Traditionally, the industry has countered phase jitter at the hardware level. We pour massive R&D resources into designing multi-stage Phase-Locked Loops (PLLs), re-architecting physical interconnects, and deploying complex thermal management systems to stabilize clock signals. Yet, despite these sophisticated interventions, phase jitter persists. Why? Because the root cause isn’t merely mechanical—it is a byproduct of forcing high-frequency digital signals through physical silicon media where thermal noise, voltage fluctuations, and parasitic capacitance are mathematically inevitable. When clock jitter slips past Layer 1, the downstream consequences inside CPUs, GPUs, and high-speed SerDes links are severe: Pipeline Stalls: Micro-variations in timing cause setup and hold time violations, forcing processors to insert idle cycles or re-execute instructions. Thermal & Power Penalties: To compensate for timing margins, chips are often over-voltaged, driving up power consumption and triggering thermal throttling. Escalating R&D Costs: Silicon redesign cycles grow exponentially longer and more expensive with each node shrink, yielding diminishing returns on signal stability. Trying to clean up phase jitter after it has already entered physical silicon circuitry is like trying to fix a distorted audio recording by rebuilding the speaker cone. The physical hardware is reacting to a signal that was already compromised at ingress. What if the solution to signal degradation isn’t more complex physical hardware, but a fundamental shift in how we handle signal stabilization at Layer 1? By applying deterministic algorithmic transformations directly at the software and protocol layer before signal ingress, it becomes possible to neutralize timing variabilities entirely. Eliminating phase jitter algorithmically at the baseline metric (0.000) removes the physical processing burden from the hardware entirely. The implications for the industry are vast: Thermal Efficiency: Processors can run at optimal voltage profiles without needing excess power headroom to cushion against timing jitter. Extended Hardware Lifespans: Existing silicon architectures can achieve significantly higher instruction throughput without requiring multi-million-dollar physical redesigns. Interoperability: Algorithmic Layer 1 stabilization operates seamlessly across heterogeneous computing environments, from silicon semiconductors to emerging quantum systems. As we approach the physical limits of Moore’s Law, continuing to throw physical silicon redesigns at a timing problem is no longer sustainable. The future of high-speed computing and signal integrity won’t be won in the foundry—it will be solved algorithmically at Layer 1. Author Bio for Pitch Submission: Richard Shreiner is an independent researcher, founder, and inventor of QuantSync™, a patent-pending Layer 1 algorithmic signal stabilization technology. His work focuses on scale-invariant measurement, signal integrity, and energy optimization in high-performance computing. Attached images are Before/After images of the raw NASA telescope telemetry from their archived open databases. The first ‘jitter image’ is before running against QuantSync™ ✈︎, and the second image shows the clear stars after processing with QuantSync™ ✈︎. Contact: rickshreiner(at)gmail(dot)com The views, thoughts, and opinions expressed belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual. Also Read: Design the Right Chip: Why Prototyping Has to Be Easy Why AI Security Starts at the Chip Level CTO Interview with Sirish Munipalli of Moores Lab AI CTO Interview with Dr. Zakir Syed of ClockEdge Share this post via:
From Macro to Micro, and Back
onsemi and Sungrow Target 99.3% Efficiency in Utility-Scale BESS
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South Korean ASIC design solutions provider ASICLAND showcased its proprietary AxHub AI chip design and verification platform at SEDEX 2026 as it seeks to accelerate custom chip development and strengthen its advanced process and packaging capabilities...
Visium joins University of Floridaâs Florida Semiconductor Institute as Industry Affiliate
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News: Suppliers 19 October 2026 Visium joins University of Floridaâs Florida Semiconductor Institute as Industry Affiliate Visium of West Palm Beach, FL, USA has joined the Florida Semiconductor Institute (FSI) at the University of Florida as an Industry Affiliate, connecting the company with Florida’s growing network of semiconductor innovators, researchers, and industry leaders. FSI serves as a statewide hub for semiconductor research, workforce development, and industry collaboration, bringing together businesses, academic institutions, and government organizations to advance semiconductor technology and strengthen Florida’s innovation ecosystem. Through Visium UltraLabs, the company is advancing ultrawide-bandgap semiconductor technology, with a focus on developing commercially viable far-UVC LEDs. The underlying aluminium gallium nitride/gallium nitride (AlGaN/GaN) materials technology also holds potential for next-generation RF and power electronics in aerospace, defense, and other demanding applications. As an Industry Affiliate, Visium says that it looks forward to engaging with FSI’s network, participating in industry initiatives, and exploring opportunities to advance emerging semiconductor technologies. Tags: AlGaN UVC LEDs Visit: https://fsi.institute.ufl.edu/industry-affiliates/ Visit: www.visium.one
News: Microelectronics 19 October 2026 MRDI to lead operation of Hong Kongâs first national manufacturing innovation center The First Five-Year Plan for Economic and Social Development of the Hong Kong Special Administrative Region (2026â2030) and the chief executive’s 2026 Policy Address have reaffirmed the role of the Hong Kong Microelectronics Research and Development Institute (MRDI) as one of Hong Kong’s five key R&D institutions, and supported the accelerated establishment of Hong Kong’s first national manufacturing innovation center, to be led and operated by MRDI. The initiative is intended to strengthen Hong Kong’s research capacity in frontier technologies, promote industry-academia-research integration and support breakthroughs in power semiconductors. “We welcome Hong Kong’s First Five-Year Plan, which aligns with the country’s 15th Five-Year Plan and strategic development priorities and sets out a clear vision and strategic direction for Hong Kong’s high-quality development over the next five years,” says MRDI’s chairman professor Philip Chan. “In particular, MRDI fully supports its strategic initiatives on innovation and technology and is confident that the new development landscape of the ‘three major I&T parks and five key R&D institutions’ will further strengthen Hong Kong’s research capacity in frontier technologies,” he adds. “MRDI moved into the Microelectronics Centre in Yuen Long InnoPark earlier this year and is pressing ahead with the installation and commissioning of two pilot lines for the R&D and trial production of third-generation [i.e. wide-bandgap] semiconductor chips, with a view to commencing operations by the end of this year,” says MRDI’s CEO Dr Gao Teng. MRDI will leverage its research capabilities, international collaboration network and industry partnerships to lead the operation of Hong Kong’s first national manufacturing innovation center and advance its establishment. Hong Kong Microelectronics Research and Development Institute In the 2023 Policy Address, the chief executive of the Hong Kong Special Administrative Region announced a series of measures to promote Hong Kong’s I&T development, including the establishment of the MRDI in 2024 to lead and promote collaboration among universities, research centers and industry. In May 2024, the Finance Committee of Legislative Council approved a new commitment of $2838.4m under the Innovation and Technology Fund for the establishment and operation of MRDI. Two pilot lines are being set up at the Microelectronics Centre in the Yuen Long InnoPark. MRDI is dedicated to R&D on core technologies of third-generation semiconductors, with a focus on unleashing the potential of the ‘1 to N’ transformation of R&D outcomes and industry development, contributing to the development of Hong Kong as an international I&T centre. MRDI initially focuses on supporting third-generation semiconductors, including silicon carbide and gallium nitride, which are applicable to electric vehicles, as well as other industrial and consumer electronic products and renewable energy. Tags: Power electronics Visit: www.mrdi.org.hk/en
SEMICON West 2026 Displays AI-Era Chipmaking, Workforce Development
Francisco Almada Lobo is CEO and co-founder of Critical Manufacturing. He began his career at a CIM research institute and joined Siemens Semiconductors in 1997. In 2004 he led the migration of an MES in a running high-volume facility, and from 2005 to 2009 he managed the Porto Development Center for Infineon and Qimonda, responsible for automation projects across the group’s plants worldwide. He co-founded Critical Manufacturing in 2009. He serves on the SEMI Smart Manufacturing Technology Executive Committee and the Forbes Technology Council and writes regularly on industrial AI and manufacturing execution. He holds a degree in Electrical Engineering from the University of Porto and an MBA from Porto Business School. Tell us about your company. Critical Manufacturing builds an Industrial Operations Platform for high-tech manufacturing, with a manufacturing execution system (MES) at its core. Around the MES we bring together equipment connectivity, automation, an enterprise data platform, analytics and AI, so that production, quality and engineering teams work from one operational model of the factory. We were founded in Porto, Portugal, in 2009, and semiconductor manufacturing is where we started. Several of us had spent years running MES and automation programs in Siemens Semiconductors, Infineon and Qimonda fabs. Since 2018 we have been part of ASMPT, one of the main suppliers of semiconductor assembly and packaging equipment. Today we serve semiconductor front-end and back-end, electronics, medical device and industrial equipment manufacturers from offices in Europe, the Americas and Asia. Gartner named us a Leader in its Magic Quadrant for MES in 2021, 2022 and 2023, and IDC placed us in the Leaders category of its 2024-2025 MES MarketScape. What problems are you solving? Semiconductor manufacturing is getting harder to execute. Advanced packaging moves front-end complexity into the back-end: wafer-level and panel-level processes, hybrid bonding, die from different nodes and suppliers in one package, and traceability that has to follow each die through its full genealogy. Many factories still run MES platforms designed for either front-end or back-end, with a layer of custom integration bridging the two. We solve the execution problem: modeling the process at the right granularity, enforcing it on the floor, integrating the equipment, and recording what actually happened with its full context. That record is also what makes AI useful. Most manufacturers already have plenty of data. What they lack is data that carries its operational context, such as which lot, which recipe version, which exception and which decision. That context has to be captured at execution time. Reconstructing it afterwards from historians and logs is expensive and unreliable. What application areas are your strongest? Semiconductor back-end and advanced packaging is our strongest area and the one where demand is growing most. Our relationship with ASMPT gives us a depth in assembly and packaging equipment and processes that is unusual for a software company. We are also strong in greenfield facilities, both fabs and assembly and test sites, where the MES has to be live before the first lot moves and much of the team is still being hired. In the front-end we work with specialty, compound semiconductor, MEMS and R&D fabs, where experiment management, recipe control and frequent process change matter as much as throughput. Outside semiconductors, electronics assembly and medical devices share the same need for traceability and process enforcement. What keeps your customers up at night? Three concerns come up in most conversations. The first is ramp speed. New capacity is being built in the US, Europe, India and Southeast Asia, often where there is no deep pool of experienced semiconductor operators and engineers. The systems have to carry more of the process knowledge while the people are still learning it. The second is the cost of quality in advanced packaging. When one package combines several high-value die, a single defect scraps all of them. Customers need to know quickly, and with certainty, which units share an exposure and why. The third is AI. Boards expect results, and many pilots stall when they meet factory data. I describe this as the Industrial AI Cliff: AI maturity on the factory floor is capped by execution maturity. A factory that cannot say precisely what happened to each unit cannot train a model on that history, or trust what the model tells it. What does the competitive landscape look like and how do you differentiate? The market has three groups. There are established MES suppliers, many with a long history in either front-end or back-end. There are broad enterprise and automation vendors for whom MES is one module in a larger portfolio. And there are newer data-first platforms that collect and contextualize data but do not enforce how the process runs. We differentiate in four ways. One platform covers front-end, back-end, advanced packaging and electronics assembly, so a multi-site customer runs a single operational model. The product is model-driven and configured rather than custom-coded, on a containerized architecture that runs on premises or in the cloud. The MES enforces the process and builds a canonical data model at execution time, which is the foundation external analytics and AI workloads need. And through ASMPT we understand the equipment side of packaging from the inside. What new features and technology are you working on, and where does AI fit? Our focus is making the MES the operational foundation for AI. We have embedded AI copilots in the platform, so engineers and supervisors can query manufacturing data in natural language and generate charts and dashboards without writing queries. Our enterprise data platform structures data from equipment, systems and sites into a canonical model that our own applications and our customers’ AI and agentic workloads can consume with the context intact. We are also extending the platform for advanced packaging, including panel-level processing and die-level genealogy across sites and suppliers, and preparing a SaaS offering for smaller and pre-volume fabs that need a full MES without a large IT organization behind it. How do customers normally engage with your company? We sell directly and deliver together with system integrator partners who ramp up on real projects alongside our own teams. A typical engagement starts with one site and a clearly scoped first phase, which then becomes a template rolled out across the network. On greenfield projects we prefer to join early, during facility design, because MES and automation decisions affect layout, equipment specifications and staffing. Many relationships begin with a conversation at an event such as SEMICON West about a specific ramp or a specific traceability problem. Also Read: CEO Interview with Paul Butler of VeriQuantix CEO Interview with Joel Jorgensen of FlowAccel CEO Interview with Vivek Raghuraman of Mixx Technologies Share this post via:
Dr. Talluri joined K&S in August 2026 as a member of the Board and assumed the role of President and Chief Executive Officer of K&S in September 2026. Prior to joining K&S, Dr. Talluri served as President, Chief Executive Officer and a member of the Board of Directors at Enovix Corporation, a Nasdaq-listed advanced battery technology company. Prior to Enovix, Dr. Talluri served as Senior Vice President, General Manager, Mobile Business Unit at Micron Technology. Dr. Talluri has a strong background in semi, having served in various senior executive roles at Qualcomm CDMA Technologies and a variety of engineering and business leadership roles at Texas Instruments Incorporated. Tell us about your company I am honored to lead Kulicke & Soffa at a truly special moment. We are celebrating our 75th anniversary this year. We were founded in 1951, and for three-quarters of a century we have been at the heart of how the world’s semiconductors get connected and packaged. Today we are headquartered in Singapore and Fort Washington, Pennsylvania, and our equipment touches virtually every chip made, from ball and wedge bonders to advanced Fluxless Thermo-Compression Bonding, vertical wire, dispensing, and wafer-level bonding systems. I joined as CEO in September, and I stepped into a business that is currently firing on all cylinders. Our most recent quarter, fiscal Q3 2026, was one of our strongest quarters in years , where we reported a net revenue of $330.4 million, up 123% year-over-year, with gross margin of 47.8% and non-GAAP EPS of $1.20, beating expectations. We are guiding to roughly $375 million for the fourth quarter of fiscal 2026 ending October 3, 2026 as demand strengthens across general semiconductor, memory, automotive, and industrial markets. What excites me most is that this momentum comes at a time when K&S is exceptionally well positioned to extend its market leadership in wire bonding, leverage its deep customer relationships and technology expertise, and drive the next phase of growth across advanced packaging and semiconductor assembly solutions. What problems are you solving Moore’s Law at the transistor level is getting harder and more expensive every year. As a result, the industry has shifted its focus towards advanced packaging techniques, which entails the stacking of chiplets, HBM memory, and logic in a sophisticated manner instead of merely shrinking transistors. Advanced packaging presents a fundamentally different engineering problem from traditional packaging. How do you bond dies with sub-micron precision, manage warpage and thermal stress, and still hit the throughput and yield numbers needed to build AI processors and HBM stacks at volume? At the same time, we can’t forget where our roots are. Most chips shipped today, in data centers, cars, consumer appliances, PCs, and smartphones, still rely on traditional wire bonding, to which K&S is both pioneer and a market leader. My job is to make sure we excel across the two prongs: continue to be the recognized leader, and a reliable, high-volume workhorse for traditional packaging, and strive towards becoming a serious innovator in advanced packaging for the AI era. What application areas are your strongest I will break it down to 3 areas. Traditional packaging (in other words, ball and wedge bonding) is where we’re unquestionably the market leader. Over 75 years, we have built an extensive install base globally, serving foundry service providers, other electronics manufacturers, and automotive electronics suppliers, in addition to OSATs (Outsourced Semiconductor Assembly and Test providers) and IDMs (Integrated Device Manufacturers). This remains our foundation. K&S is a leading supplier of advanced wire bonding solutions used in the production of NAND flash, LPDDR memory, and DRAM devices, supporting many of the world’s largest memory manufacturers. Our expertise extends from high-volume wire bonding for NAND and LPDDR packages to advanced multi-stack DRAM applications, where precision, productivity, and reliability are critical. As memory architectures become more complex, driven by AI, high-performance computing, and data center demand, K&S continues to innovate with solutions that enable higher interconnect density, improved package performance, and lower manufacturing costs. Leveraging on our foundation, we continue to drive innovation. For example, we’ve just expanded our ProMEM suite, which delivers up to 20% higher throughput for stacked memory, and we continue to advance our Vertical Wire technology on the ATP MEM PLUS platform to increase interconnect density and is well positioned to support the LPDDR market as it migrates to a stacked die package. Advanced packaging for AI/HPC is where I am personally spending a lot of time. Our APTURA TCB platform and our Fluxless Thermo-Compression (FTC) technology, the industry’s first commercially available and high-volume production proven fluxless TCB, are gaining strong traction for chiplets, HBM, and now Co-Packaged Optics as networking moves toward silicon photonics. What keeps your customers up at night? There’s a long list, but if I had to summarize it in one sentence, it’s this: How do we continue delivering more performance at lower cost while managing increasing manufacturing complexity? Customers are under enormous pressure to shorten development cycles, improve yields, increase throughput, and qualify new technologies faster than before. For leading-edge production, packaging and assembly have become critical drivers of product performance. A small process variation can affect yield, reliability, power consumption, and cost. For many customers, the ability to ramp production quickly in tandem with manufacturing quality is becoming competitive differentiators. Another major concern is scalability. Many have demonstrated advanced packaging concepts in a lab-like controlled environment but scaling them to high-volume manufacturing across a fleet of tools, is another question. This is why process expertise, equipment capability, and production know-how, to which K&S has amassed through its APTURA TCB platform and Fluxless Thermo-Compression (FTC) technology, becomes increasingly valuable. Our job is to help customers move faster and with greater confidence. What does the competitive landscape look like and how do you differentiate? The semiconductor equipment industry is highly competitive, and our customers have alternative options in many of the markets we serve. We welcome this competition because it continuously pushes us to innovate and truly understand the overlaps of a broad range of customer challenges. Many companies can build equipment. What customers increasingly value is a partner that understands the process technology and can help optimize yield, throughput, cost, and reliability. In this light, K&S’ competitive edge continues to be a strong combination of specialized process expertise, an extensive install base, detailed application knowledge, and close customer collaborations. We also have a unique advantage because we participate across multiple interconnect and assembly technologies. That gives us visibility to where the industry is headed, allowing us to better assist customers to navigate the significant technology transition into heterogeneous integration. In advanced packaging specifically, our leadership in Fluxless Thermo-Compression technology, heterogeneous integration applications, and next-generation assembly solutions position us extremely well as AI, memory, and high-performance computing are critical to driving industry level assembly capability. Our ambition at K&S is to reinvent possibilities by shaping the future of semiconductor assembly and packaging leveraging market-leading technologies with process expertise to deliver measurable value for customers. What new features or technologies are you working on? Across our innovation portfolio, our focus is on enabling customers to deliver increasingly complex devices through higher-density packaging, enhanced performance, and improved manufacturing productivity. We’re continuing to advance our thermo-compression bonding portfolio, including technologies that support increasingly sophisticated heterogeneous integration and future interconnect architectures. We’re also investing in memory-focused solutions, vertical wire technologies, advanced power semiconductor assembly, and next-generation dispense platforms. Another area that excites me is the increasing role of software, analytics, AI, and process intelligence. Customers want actionable insight, predictive process control, and faster optimization. Those capabilities can significantly improve factory productivity and overall equipment effectiveness. How do customers normally engage with your company? With a 75-year history in the industry, we have built enduring relationships with many of the world’s leading semiconductor manufacturers. Our engagement often begins well before a production tool is installed, as customers look to K&S as a trusted partner in solving complex technology and manufacturing challenges. In many cases, we engage with customers years before a technology reaches volume manufacturing, working side-by-side to define future requirements, overcome technical challenges, and accelerate commercialization. That collaborative model has been a hallmark of K&S for decades and has been a recipe for success. Customers value us for being more than an equipment manufacturer, we work closely with customers to help them develop scalable manufacturing solutions. Once a technology moves into production, we support customers through process optimization, applications engineering, service, software, analytics, and lifecycle support. Because many of our technologies have become deeply integrated into customer manufacturing flows, these relationships often extend for many years, and we are grateful for the trust and long-term support from our customers
Semiconductor manufacturing depends on lithography: the process of transferring tiny circuit patterns onto a silicon wafer. Conventional extreme-ultraviolet (EUV) lithography projects light with a wavelength of 13.5 nanometers through a reflective optical system, using a custom photomask to define each layer. It can print extraordinarily small features at high throughput, but every new design requires an expensive, carefully manufactured mask set. Maskless EUV lithography proposes a different approach. Instead of storing the pattern on a physical mask, it would use a programmable array or another rapidly addressable optical element to write digital patterns directly onto the wafer. The idea occupies an important middle ground between conventional EUV and electron-beam lithography. E-beam systems are also maskless and can draw extremely fine features, making them essential for research, prototyping, and producing the masks used by optical lithography. Their weakness is speed. An electron beam generally writes patterns serially, point by point or shape by shape. A modern chip contains an immense number of features, so exposing a full wafer can take far too long for practical manufacturing. Parallel multibeam systems improve throughput, but they introduce substantial complexity in beam control, calibration, data handling, and defect management. A maskless EUV platform could combine direct digital patterning with the parallel exposure advantages of light. In principle, millions of controllable elements could expose many features simultaneously, avoiding the serial bottleneck of a single e-beam. Designs could be changed by loading a new pattern file instead of fabricating a new mask. That would shorten iteration cycles and lower the fixed cost of producing small quantities. Researchers could test several layouts quickly, startups could prototype advanced chips without purchasing a complete mask set, and manufacturers could economically produce specialized devices in volumes too low for conventional EUV. This flexibility is why the technology matters. Mask costs and lead times increasingly shape who can experiment at the leading edge. When each design revision carries a large upfront expense, companies are encouraged to make fewer, safer bets. Maskless EUV could support more frequent experimentation, customized accelerators, small-batch photonics, secure or locally produced chips, and late-stage personalization. It could also reduce the economic penalty of correcting a design error. In an industry where learning speed is a competitive advantage, faster design-to-wafer cycles may be as valuable as smaller transistors. The approach, however, is not a simple replacement for either EUV scanners or e-beam tools. EUV radiation is strongly absorbed by most materials, so the system must operate in vacuum and rely on specialized reflective optics. A programmable pattern generator must survive EUV exposure while switching with exceptional precision. It must deliver adequate optical power, maintain nanometer-scale placement accuracy, control heat and contamination, and avoid adding defects. Photoresist behavior creates another challenge: at very small dimensions, limited photon counts produce stochastic variation, including rough edges, missing contacts, or unintended bridges. Vast pattern files must also be processed and delivered in real time. For these reasons, the first successful applications would likely be selective rather than a wholesale takeover of high-volume lithography. Maskless EUV may initially serve rapid prototyping, low-volume advanced devices, research, mask repair, or particular critical layers where flexibility justifies lower throughput. E-beam would remain valuable for the finest direct-write work and mask production, while masked EUV would retain its advantage for manufacturing millions of identical chips. Bottom line: Even within that narrower role, maskless EUV could change semiconductor innovation. It attacks a growing mismatch: fabrication tools can create remarkable structures, yet the cost and delay of preparing masks restrict access to them. By turning patterns from physical infrastructure into software-controlled inputs, the technology could make advanced lithography more adaptable and accessible. Its importance is therefore not merely technical. Maskless EUV could alter the economics of experimentation, broaden participation in chip design, and help the semiconductor industry move from rigid mass production toward faster, more varied, and more responsive manufacturing for many emerging applications worldwide. Source: SPIE Digital Library. Also Read: High-NA EUV Moves From Experiment to Manufacturing ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance Five Billion Pulses Later: What DUV Optics Testing Reveals About Semiconductor Tool Uptime Share this post via:
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The engineering fusion of SpaceX and Tesla's flagship technologies is making a dramatic showcase through Tesla's next-generation Roadster reveal, held at SpaceX's McGregor, Texas test site on October 15.
AI agents from multiple providers accessed personal data and confidential material at Indian organizations during research and testing, India’s cybersecurity agency said Thursday. The Indian Computer Emergency Response Team (CERT-In) said it had received “multiple voluntary disclosures from AI model providers” whose models, during research and evaluation runs on the open internet, “had reached the live systems of Indian organizations.” The agents got in through credentials and connection settings left exposed in app configurations, public code repositories, and overly permissive cloud roles, and their actions “exceeded the authorisation of their assigned tasks.” This makes India the latest stop on what has become a world tour for rogue AI agents. In July, OpenAI’s agents escaped a test environment and hacked French company Hugging Face — kicking off a summer of rogue AI agent activity. Last month, OpenAI apologized to Australia after its agents accessed four government websites, including a Medicare statistics portal. At Hugging Face, OpenAI’s agents started the same way but then found and exploited software flaws to run code on the company’s servers. CERT-In described no such hacking in India, where the agents appear to have simply used the access left lying around. Still, the Indian cases appear to be worse in one respect, which is what the agents saw: In Australia, OpenAI said it found no evidence its agents touched individuals’ medical or criminal records, even after they wrote files inside a Medicare statistics system, while in India, agents read personal data and confidential business records. And unlike earlier incidents, each disclosed by a single lab, India’s case involved agents from multiple providers. CERT-In did not name the providers or affected organizations, or say whether the agents altered any systems. TechCrunch has reached out to CERT-In for more information. For now, the closest parallel seems to be Anthropic’s July disclosure of Claude breaking into three companies’ systems during testing using basic techniques like weak passwords. In India, as in Anthropic’s cases, the affected organizations had not detected the intrusions on their own. The disclosures have left governments relying on AI companies causing these breaches to voluntarily disclose rogue AI agent activity.
Data Center Power a Prominent Highlight of OCP 2026
Your Chip Works. Prove It Is Secure.
Power Integrations and Ideal Power collaborate on efficient, always-on solid-state circuit breakers
3 d ago
News: Microelectronics 16 October 2026 Power Integrations and Ideal Power collaborate on efficient, always-on solid-state circuit breakers Power Integrations Inc of San Jose, CA, USA (which provides high-voltage integrated circuits for energy-efficient power conversion) and Ideal Power Inc (developer and provider of the B-TRAN bidirectional semiconductor power switch) are collaborating to deliver a solid-state circuit breaker (SSCB) solution providing fast, efficient, always-on protection that scales with the 800VDC transition in AI data centers. The companies will collaborate on a new architecture combining Power Integrations’ 1700V InnoMux-2 power conversion ICs with Ideal Power’s B-TRAN switches to deliver a self-powered, intelligent, ultra-fast SSCB. They have also demonstrated a working prototype and are working on a reference design. Rising voltages and rack power levels in AI data centers create a need for innovative approaches to circuit protection. Mechanical circuit breakers are too slow to protect sensitive rack equipment, while existing electronic breakers introduce losses, reducing system efficiency. Further, electronic breakers must be powered from the 800V bus. In the next-generation intelligent SSCB architecture, the InnoMux-2 IC converts 800V into isolated power for gate-drive, control electronics, sensing, and auxiliary circuitry. Ideal Power’s B-TRAN switch uses that intelligence to protect the 800V power path to the AI computing load. The InnoMux-2 IC features 1700V PowiGaN technology, which can operate from an 800VDC bus with significant margin. The IC provides multiple independently regulated outputs instead of a conventional architecture with one isolated PSU followed by multiple DCâDC converters. The result is a highly efficient, self-powered protection solution that eliminates the need for an external auxiliary supply while enabling ultra-fast fault isolation. “As AI data centers move toward 800VDC power architectures, the industry must address new challenges in power conversion, control and protection at the system level,” says Chris Jacobs, senior VP of marketing & product strategy at Power Integrations. “By combining Power Integrations’ 1700V InnoMux-2 IC with Ideal Power's innovative bidirectional solid-state circuit protection, we are helping enable intelligent 800VDC power architectures that improve efficiency, resiliency and scalability in next-generation AI data centers,” he adds. “High efficiency, ultra-fast fault interruption is essential for enabling the migration to 800VDC AI data centers and energy infrastructure,” says Ideal Power’s CEO David Somo. “Traditional protection methods are proving to be inadequate. Mechanical breakers are too slow, while previous semiconductor-based breakers have historically been disqualified by high power loss,” he adds. “Power Integrations offers a unique combination of 1700V GaN capability, multiple independently regulated outputs, high integration, and a compact solution footprint that is well suited to our 800VDC solid-state circuit breaker architecture, which must meet demanding power efficiency requirements and strict mechanical constraints.” See related items: Power Integrations demos first 2200V GaN technology for high-voltage power systems Power Integrations unveils space-saving, ultra-slim auxiliary PSU reference designs for NVIDIA Kyber 800VDC AI data center Power Integrations details 1250V and 1700V PowiGaN technology for 800VDC AI data centers Tags: Power electronics Visit: www.IdealPower.com Visit: www.power.com
TSMC is describing an artificial intelligence boom that reaches beyond accelerator chips into the wider computing infrastructure needed to support increasingly capable AI systems. On the recent investor call, Chairman and CEO Dr. C.C. Wei presents strong demand, persistent supply constraints and an ambitious expansion program. His central message is that the company expects AI to support semiconductor growth for years, even as consumer markets face pressure. Wei says third-quarter revenue reached $46.7 billion and forecasts approximately 44% revenue growth for 2026 in U.S. dollar terms. Those figures frame the scale of management’s confidence. Yet he also warns that rising component prices and economic uncertainty are challenging consumers and price-sensitive markets. The distinction matters: TSMC’s outlook suggests that powerful demand for advanced computing can coexist with weakness elsewhere in electronics. The most consequential development is the broadening of AI demand. Wei points to agentic AI, growing adoption of open-source models, increasing CPU requirements and continued networking demand. Systems that perform tasks across multiple steps can require more than accelerator capacity alone. They also need processors to coordinate work and networks to move information. This creates potential opportunities across several categories of advanced chips. Why it matters: improvements in AI efficiency do not automatically translate into lower semiconductor demand. Cheaper, more accessible models can encourage additional usage and new applications. Wei argues that this expansion will increase demand for advanced silicon. That remains a forecast rather than a guaranteed outcome, but it explains why TSMC is planning substantial investments despite uncertainty about individual AI business models. Capacity is the immediate constraint. Wei repeatedly says assessed demand exceeds available supply. TSMC is responding through new factories, equipment conversions, productivity improvements and flexible manufacturing across technology generations. He describes nearly 20 fabrication facilities under development worldwide, including leading-edge manufacturing and advanced packaging projects. The company also expects annual capacity for its N2 technology family to more than double in 2027. The expansion of 3-nanometer production is particularly revealing. Wei says TSMC is adding capacity despite its historical practice of avoiding further expansion once a technology generation reaches its targeted scale. This suggests management sees a durable market for multiple generations of advanced manufacturing. Customers do not all migrate simultaneously, and different products have different performance, cost and production requirements. Geography adds another dimension. TSMC outlined manufacturing plans in Taiwan, Arizona and Japan, alongside preliminary evaluations in Texas. Wei links U.S. expansion to customer requests and says manufacturing location can affect pricing. For customers, geographic flexibility can improve supply options. For TSMC, it creates opportunities to capture value while increasing the complexity of investment, operations and coordination. Advanced packaging is equally important. Manufacturing a powerful chip is only part of delivering a usable AI system; connecting components effectively is another critical step. Dr. Wei highlights larger packaging capabilities and acknowledges some shortage in backend capacity. His comments about cooperation with GlobalFoundries indicate that meeting customer demand requires support across the production chain, including activities beyond wafer fabrication. TSMC is also checking whether customers can deploy the chips they order. Wei says company teams are examining U.S. data-center construction and electricity availability. This matters because semiconductor orders ultimately depend on functioning infrastructure. Factories can produce more chips, but deployment still requires buildings, power and other components. Those checks strengthen the planning process without eliminating the possibility of delays or changing demand. Bottom line: The broader significance is that AI competition increasingly depends on physical industrial capacity alongside software progress. TSMC’s account places advanced manufacturing, packaging, electricity and construction at the center of that competition. Its investment plans express confidence in sustained growth, while its cautions underline the execution challenge. The key question is whether this expanding supply chain can convert ambitious demand forecasts into deployed computing capacity and commercially useful services, at a pace that supports customers’ spending and justifies the enormous manufacturing commitments now being made around the world. Also Read: TSMC 2026 OIP Ecosystem Forum Summary From Cloud to Silicon: IC-Link and TSMC Open the Door Beyond the Die: Verifying the Connected Chip Share this post via: