Edge AI for Real-Time Systems, the Edge Computing Energy Problem, PCIe 6.0 High-Radix Switches: Embedded Week Insights
NVIDIA GB10/N1X SoC Yesterday we got to look at our first device based on NVIDIA’s RTX Spark SoC: Microsoft’s Surface Laptop Ultra. The latter, the most premium Surface Laptop yet, is the tip of the spear in a broader push within the Windows ecosystem to increase adoption of Arm-based processors. This week NVIDIA is the pole driving that spear tip, with the launch of the RTX Spark. The RTX Spark launch has been something of a long time coming for NVIDIA. I do not just mean that philosophically. NVIDIA has shipped the underlying GB10 SoC in Linux systems for around a year now, and if the rumors are to be believed, it intended to ship it even sooner. So NVIDIA, its partners, and end-users have been waiting a long time to see what the company’s latest Arm SoC can do when driving a Windows system. Microsoft Surface Laptop Ultra-Front Angled 3 This week, we finally get answers to those questions. Alongside the Surface Laptop Ultra, another half-dozen laptops have been released this week based around the RTX Spark, and there is even a Windows mini-PC (Microsoft’s Surface RTX Spark Dev Box) for good measure. Many of these device manufacturers are taking a similar tack to Microsoft and focusing on developers and content creators, a decision not surprising given what we have seen of GB10 thus far, while others have assembled laptops aimed at the broader consumer market. As a result, although the RTX Spark is a high-end SoC in the vein of, say, AMD’s Ryzen AI Max series (Strix Halo), it is being pitched to a wider user base than we saw with just Microsoft’s laptop. With that in mind, we wanted to take a moment to briefly run through the RTX Spark, both the chip and the wider platform it defines. What are the similarities and differences between the DGX Spark and RTX Spark platforms? How is NVIDIA promoting its SoC as a new-to-you product for the consumer market? For the answer to that and more, let us dive right in. NVIDIA RTX Spark N1X Architecture: A GB10 Refresher First, let us start with the architecture of the RTX Spark. Officially dubbed the “RTX Spark N1X” by NVIDIA, leaving room for future chips in the RTX Spark family, the N1X is the consumer-facing name of our tried-and-true friend in the Linux mini-PC market: the NVIDIA GB10. This is NVIDIA’s latest Arm SoC, and what is really their first SoC in several years that is aimed at end-user systems. GB10 is a high-end design that has seen NVIDIA leverage most of its recent CPU and GPU technologies in a single low-power chip. NVIDIA likens it to a scaled-down version of its Grace Blackwell server architecture, and while it is not an exact scale-down replica, it is not far off the mark, either. NVIDIA offered a deep dive into the GB10’s architecture back at Hot Chips 2025, and most of what we learned back then still applies to the RTX Spark N1X as well. At a high level, GB10 is a joint project between NVIDIA and MediaTek. The chip is comprised of two chiplets. There is a CPU and memory chiplet (the S-dielet) designed by MediaTek, and a GPU chiplet (the G-chiplet) designed by NVIDIA. Notably, both chiplets are built on a TSMC 3nm process, which at the time of GB10’s launch was the most cutting-edge node at the fab and newer than the node used for NVIDIA’s Blackwell-architecture GPUs or its Grace CPU. So, in some respects, GB10 is the most advanced Blackwell architecture chip designed by NVIDIA. RTX Spark N1X CPU Tile On the CPU die, MediaTek designed a chiplet with four groups of CPU cores, organized into two clusters. The performance cores include a whopping 10 Arm Cortex-X925 cores across the clusters. Meanwhile, the efficiency cores include an equally whopping 10 Arm Cortex-A725 cores across the chip. Each cluster has its own 16MB L3 cache. This is an off-the-shelf core design from Arm’s 2024 Cortex lineup (not based on NVIDIA’s Grace), so while MediaTek has its own layout, there are no architectural differences from Arm’s stock designs. That NVIDIA is launching a chip based on 2024 CPU cores in 2026 means the RTX Spark N1X enters the market a bit behind the curve in CPU technology, with performance repercussions. In practice, GB10 emphasizes multi-threaded performance over single-threaded performance, especially since this design does not push high CPU clock speeds. MediaTek’s die also includes the system’s memory controller, which is a key element of its performance. MediaTek equipped the chip with a wide 16-channel, 256-bit LPDDR5X memory bus, making it one of just a handful of (non-Apple) consumer chips to use such a wide memory bus. The wide memory bus not only lets the chip tap into 300GB/second of memory bandwidth (using LPDDRX-9400), but also lets it connect to up to 128GB of memory in its current configuration. NVIDIA GB10 Specifications One benefit of NVIDIA’s RTX Spark technology briefings is that they have provided the cleanest GB10 floorplan to date, which lets us see how much space the memory controllers take up. It is a lot of space, though less than you might think given everything else going on. Surprisingly, the CPU die also holds the chip’s NVIDIA-designed display controllers, even though the GPU hardware itself sits on the other die. This is because display controllers are best placed close to memory controllers for bandwidth and power reasons, and here they sit directly next to one of the memory controller blocks. This is also where all of the general-purpose I/O is located, most notably the chip’s PCIe lanes. Finally, the chip implements one final piece of NVIDIA IP with its NVLink-C2C interface. The chip-to-chip interface links the two chiplets in GB10, similar to how it connects Grace CPUs to Blackwell GPUs in server-grade GB200/GB300 systems. For GB10, this is a 600GB/second link, making it roughly twice as fast as the memory controllers. RTX Spark N1X GPU Tile Meanwhile, the other half of GB10 is the NVIDIA-designed G-chiplet. This is dedicated entirely to graphics, and houses a relatively powerful implementation of NVIDIA’s Blackwell GPU architecture. Specifically, this is a 48 SM Blackwell configuration, affording 6144 CUDA cores overall. In the context of NVIDIA’s other offerings, this is equivalent to NVIDIA’s GeForce RTX 5070 in terms of hardware, though the latter has the benefit of over twice as much memory bandwidth thanks to its use of GDDR7. To be clear, this is a full Blackwell graphics implementation. This is not just a scaled-down version of NVIDIA’s server designs. That is, it has a full suite of graphics features alongside its CUDA cores and tensor cores, including ray tracing hardware, texture units, ROPs, and everything else needed to draw a pixel. This means that GB10 has the hardware needed to support NVIDIA’s full suite of graphics features (DLSS, etc.), which they expect to be a big differentiator in the consumer space. GB10: A Successful Collaboration Between NVIDIA and MediaTek NVIDIA has previously hailed GB10/N1X as being a successful collaboration between the two companies. Whether we will see something like this again in the future is still up in the air, but the fact that this is not a monolithic chip designed solely by NVIDIA is quite notable, given their last 15 years of designing their own Arm SoCs for Tegra, DRIVE, Jetson, and other NVIDIA offerings.
Elektrobit and Microchip Simplify AUTOSAR Integration
Summary: AMD Helion lets customers tailor CPU core density, performance and power to agentic workloads, with CPU-only configurations for hyperscale deployments and integrated CPU/GPU configurations for enterprises AMD Helion combines open hardware and software with an integrated token router that directs agents’ model calls across frontier and open-source models AMD introduced the AMD Helion agentic AI rack, an open blueprint for agentic AI infrastructure based on an Open Compute Project spec-design and powered by AMD compute.Building on the open-platform approach of the AMD Helios rackscale solution, AMD Helion is designed to provide partners and customers with the flexibility they need for agentic AI infrastructure. With AMD Helion, customers can match CPU performance, core density and power with GPU acceleration for the work their AI agents perform. “Agentic AI is not a single workload. It spans personal agents, enterprise applications, code execution and complex workflows, each with different compute requirements,” said Dan McNamara, SVP and GM, compute and enterprise AI, AMD. “To do that takes optimized compute and infrastructure that can adapt to different workloads. With AMD Helion, we are bringing AMD EPYC performance, open software and flexible rack designs together so our partners can build systems around customer needs and make efficient use of available power.” AMD Helion’s OCP spec-based rack blueprint supports open software and can come in flexible configurations, including liquid- and air-cooled versions, allowing customers to create virtually any configuration needed for their needs. Some examples of this include: A CPU-only rack powered by 6th Generation AMD EPYC processors that can support up to 32,768 CPU cores. This rack is designed for hyperscale customers, providing dedicated capacity for agent execution and connections to separate model inference infrastructure An all-in-one rack that combines AMD EPYC CPU nodes, AMD Instinct MI350P GPU nodes and general-purpose compute on one platform. This rack is designed to provide partners and customers an all-in-one concept for enterprise agentic AI AMD Helion enables customers to deploy agentic AI in the IT infrastructure they already have, turning existing investments into a foundation for new AI capabilities. Partners can tailor CPU and GPU configurations to customer workloads, matching agent execution, model inference and supporting compute to each deployment’s performance, power and cost requirements. AMD plans to contribute the AMD Helion spec to OCP, making it available to the community for further development and adoption. AMD Helion agentic rack configurations are currently under development with ecosystem partners and are planned to be available in November 2026. AMD is helping shape the next phase of AI infrastructure through open, flexible platforms, a broad portfolio of workload-optimized compute and collaboration across the ecosystem. AMD Helion brings that approach to agentic AI, helping partners match software and compute to the work agents perform and giving customers flexibility to scale as their requirements evolve. “Agentic AI is changing what customers need from their infrastructure. It’s not just about compute performance, but how the entire system is connected, managed and secured. Architectures like AMD Helion, combined with Cisco’s full-stack infrastructure capabilities, can give customers greater flexibility to deploy, operate and scale agentic workloads into their environments as their needs evolve,” said Jeremy Foster, SVP and GM, Compute, Cisco. “Dell PowerRack gives customers choice without compromise, and our support for AMD Helion Agentic Rack Reference Design extends that promise to the next generation of agentic AI. By combining AMD’s rack-scale architecture with Dell’s proven engineering expertise, along with the flexibility to extend deployments with Dell PowerRack for Networking and Storage, we’re giving customers a complete, validated path to deploy agentic compute at scale with the manageability and reliability they expect from Dell,” said Arun Narayanan, SVP, compute and networking, Dell Technologies. “Hon Hai Technology Group continues to deepen its collaboration with AMD on AI infrastructure, supporting the new AMD Helion Agentic AI Rack reference design. Built on an open architecture, the platform combines 6th Generation AMD EPYC processors with flexible CPU and GPU configurations to address hyperscale data center and enterprise Agentic AI workloads. The Group will continue to leverage its strengths in rack-level system integration and global manufacturing, working with ecosystem partners to advance rack-scale Agentic AI solutions and accelerate next-generation AI infrastructure deployment,” said Hon Hai, Technology Group. “Next-generation AI workloads require scale, efficiency, and flexibility that open, rack-scale architectures deliver, as demonstrated by our recent customer agreement to deploy AMD Helios. For decades, HPE and AMD have jointly championed open standards, and we are continuing to advance those efforts with AMD Helion. Together, we are ushering in the next era of AI with open large-scale systems, enhanced with air-cooled and direct liquid-cooled networking, supported by decades of HPE expertise and innovation,” said Trish Damkroger, SVP and GM, HPC & AI infrastructure solutions, HPE. “As agentic AI moves into production, customers need flexibility in how and where they deploy it. That’s at the core of the Lenovo Hybrid AI Advantage, and AMD Helion will give added versatility to meet customers where they are and support the workloads they want to run,” said Scott Patti, VP, infrastructure solutions group, Lenovo. “Agentic AI will require a range of system designs to serve different customer needs. AMD Helion provides an open blueprint that gives QCT the flexibility to tailor compute configurations and bring system design and customization expertise to those requirements,” said Mike Yang, president, QCT. “Supermicro is accelerating the deployment of next-generation agentic AI infrastructure by bringing AMD’s Helion – the open, ORv3 compliant rack-scale architecture to market through our Data Center Building Block Solutions (DCBBS). With our proven expertise in OCP accepted rack-scale design, integration, liquid cooling, software, and deployment services, we transform advanced Agentic AI architectures into production-ready solutions. Together with AMD, we enable customers to deploy faster, scale efficiently, and accelerate time to online for agentic AI,” said Vik Malyala, CBO, Supermicro. “AMD Helion provides an open, flexible foundation for agentic AI infrastructure. Wiwynn is excited to collaborate with AMD, bringing our expertise in rack-level integration and advanced cooling to help hyperscaler customers tailor systems that meet the demanding workloads, power requirements, and data center environments of the agentic AI era,” said William Lin, president and CEO, Wiwynn.
From Spooky Action to Quantum Internet: Communication Takes to the Air
Solving the Edge Computing Energy Problem
The final day of TechCrunch Disrupt 2026 has arrived, and the week is ending on a high note. As 10,000+ founders, investors, and technology leaders gather at San Francisco’s Moscone West, Day 3 features some of the conference’s most practical and future-focused discussions. Explore sessions covering the next wave of AI innovation, startup growth strategies, fundraising, emerging technologies, and lessons from the entrepreneurs and investors defining the future of tech. Add in Startup Battlefield excitement, peer networking, and countless opportunities for serendipitous connections, and it’s one final opportunity to maximize your Disrupt experience. Don’t miss your chance to be part of the conversations everyone will be talking about after Disrupt. Grab your pass now at 75% off the original ticket price and join us for Day 3. Day 3 highlights Registration hours: 8:00 a.m. – 3:30 p.m. Stop by the registration desk in the Level 1 lobby of Moscone West to register in person or pick up your scannable event badge. The badge features Klik technology, which makes it easy to exchange contact information with people you scan your badge with. Using the event app, you can access and keep those contacts even after the event ends. Expo Hall: 8:00 a.m. – 3:30 p.m. Explore 320+ exhibiting startups showcasing cutting-edge technologies across industries. This is the center of Disrupt, where 10,000+ attendees converge to discover new breakthroughs and spark new connections. Haven’t registered yet? You still can — but don’t wait, or you will miss out. Grab your ticket now and walk straight into the action: six industry stages, interactive roundtables, Q&A breakouts, hundreds of exhibiting startups, investor-founder meetings, AI-powered matchmaking networking, and Side Events lighting up the Bay Area tech scene all week long. Image Credits:Eric Slomonson, The Photo Group Pitch Showcase Stage Make your way to the Pitch Showcase Stage at the back of the Expo Hall to experience one of the most electrifying formats on the conference floor: rapid-fire, one-minute lightning pitches from some of the most promising startups representing their home countries and regions. Pitch Showcase Stage Startup Battlefield 200 Fast Pitches – Health Startup Battlefield 200 Fast Pitches – Consumer Onstage programming Check out the full Disrupt agenda for all of today’s sessions. Builders Stage Yes, It’s Hard to Be a Founder: An Honest Conversation: Nell Daly, Revenge Capital; David H. Rosmarin, Harvard Medical School; Jack Withinshaw, Airspeeder M&A Is Now an Early-Stage Strategy: Karl Alomar, M13; Lindsey Mignano, Mignano Law Group; Ryan Yi, Onchain Group How to Create Viral Growth and Capitalize On It: Zach Yadegari, Cal AI The First 90 Days: How Startups Build Toward $10M ARR: Luke Arno, Lovable; Ben Broca, Polsia; Tomasz Tunguz, Theory Ventures Winning Pre-Seed Without a Product: Puneet Agarwal, True Ventures; Austin Clements, Slauson & Co.; Sandhya Venkatachalam (Axiom Partners) Building AI Startups Worth Betting On: Nader Khalil, Nvidia; Sydney Sykes, Nvidia Ask the Investors: Karl Alomar, M13; Stacy Brown-Philpot, Cherryrock Capital; Dayna Grayson, Construct Capital Disrupt Stage What Comes After the Smartphone?: Panos Panay, Amazon Can Social Start Over?: Toni Schneider, Bluesky Social; Rose Wang, Bluesky Social Can You Bank Your Biology?: Dr. Nabiha Saklayen, Cellino After Startup Battlefield: What Happens Next?: Piotr Byrski, Molecule.one; Kevin Damoa, Glīd; Demetri Maxim, Nephrogen Startup Battlefield Final: Karl Alomar, M13; Stacy Brown-Philpot, Cherryrock Capital; Chi-Hua Chien, Goodwater Capital; Dayna Grayson, Construct Capital; Alexa von Tobel, Inspired Capital Everyone Can Build Software Now. What Happens Next?: Amjad Masad, Replit Beyond the Check: The Power of Access: Bruce Lee, Keebeck Wealth Management; Mark Wahlberg, MUNICIPAL Announcing the Winner of the Startup Battlefield 2026 Breakout Stage Build an AI Product in the Age of Agents (Certification Included): Dr. Marily Nika, AI Product Academy Building a Growth Engine in the AI Era: Lessons from a Bootstrapped Unicorn: Patrick Burke, Hostinger Physical AI Isn’t a Model Problem. It’s an Execution Problem: Ethan Batraski, Venrock; Ivan Poupyrev, Archetype AI; Ian Rountree, Cantos Talent as the Operating System: How High-Performance Teams Scale in the AI Era: Nomi Khedawala, Reddit Industry Stage — AI The Agent Security Problem Nobody Is Talking About: Gavriel Cohen, NanoCo; Ric Smith, Okta Rewriting SaaS: Why AI Breaks the Old Business Model: Cathy Gao, Sapphire Ventures; Aaron Jacobson, NEA; Barr Moses, Monte Carlo Before You Let AI Do the Job, How Do You Know It Actually Can: Irene Solaiman, Hugging Face The $63 Billion Case for Storagemaxxing Your AI Stack: Kevin Cochrane, Vultr; Jake Lee, L2 Point Management; Pinaki Mukherjee, Wasabi Technologies; Stephanie Walter, HyperFRAME Research What Comes After the Chatbot: Alexander Embiricos, OpenAI The GTM Engineer: How AI Created Tech’s Next Big Job Category: Kareem Amin, Clay Model Behavior: How Top Startups Get Real Value From AI Adoption: Kareem Amin, Clay; David Hershey, Anthropic; Grant Lee, Gamma Proxy, Host, Operator: Who Can Read Your Agent’s Prompts?: Richard Rizk, Blackbox AI Securing the AI Enterprise: Why the Cloud Just Got a Lot More Complicated: Rudy Mitra, Amazon Web Services; Katie Moussouris, Luta Security; Wendy Nather The Enterprise Isn’t Broken. Your Assumptions About It Are: Arsalan Tavakoli-Shiraji, Databricks Image Credits:Slava Blazer Photography Roundtables I Built Before the Internet. AI Is Different: James Joaquin, Obvious Ventures AI-Native Won’t Work for the Enterprise: Naren Krishna, Balerion; Travis Skelly, Pruven Capital Sandboxes are Dead, Give Your Agent a Private Cloud: Praveen Akkiraju (Insight Partners), Vasek Mlejnsky (E2B) Berkeley Connect: Experience the World’s #1 Startup Ecosystem: Maryanne Alhallak (Lumeria), Anthea Guo (Lumeria), Keith McAleer (UC Berkeley SCET) The Next Logistics Stack: Autonomy, Infrastructure and National Resilience: Kofi Asante (Bluecore Energy), Kevin Damoa (Glīd) Autonomous Intelligence: Investing in the Companies Redefining Work: Parul Singh (645 Ventures) AI Infrastructure & Power & Decarbonization in Dialogue: Investor + CVC Perspective: Jane Ge (Vectors Capital), Elias Habbar-Baylac (Cisco) How Not to Ruin Your Co-Founder Relationship: Dr. Jessica Gold (Bliss Science), Tevye Krynski (Digital Wisdom) From Silicon to Software: Building Efficient AI Inference at Scale: Anush Elangovan (AMD), Junchen Jiang (Tensormesh) Still time to join Disrupt 2026 There’s still some time left to register for your pass and explore all these activations. Get your ticket now at 75% off the original prices. Tickets are available through this final day. Secure yours now and be part of the future of tech. Do not wait, or you’ll have to wait until next year.
Microchip Unveils PCIe Gen 6 and NVMe Devices for Data Centers
Axiado, Arm Integrate AI Security into AGI CPU Servers
Blog written by Nvidia and published October 12, 2026 As AI factories grow from megawatts to gigawatts, building them takes more than advanced computing. Open standards are helping the industry scale AI infrastructure faster, more efficiently and more reliably. At the Open Compute Project (OCP) Global Summit, taking place in the San Jose McEnery Convention Center, Nvidia announced new partnerships and contributions aimed at creating a common foundation for next-generation AI infrastructure.Nvidia contributed key Nvidia Vera Rubin rack and compute tray designs to OCP through the open Nvidia MGX architecture, giving system builders a common foundation for developing next-generation AI factory infrastructure. Together, these efforts span the AI factory itself, the utility grid that powers it and the rack-scale architecture at the heart of modern accelerated computing. Nvidia and Partners Announce Open Architecture Advances At the OCP event, Nvidia and partners made a handful of announcements: Nvidia and hyperscalers published open standards for next-generation AI factories, including AI factory design standards and grid resilience Nvidia launched new open source software components for Nvidia DSX AI Factory Meta and Nvidia advanced open AI networking with Nvidia Spectrum-X Ethernet SuperNIC and Spectrum-6 innovations Visionbay introduced an 800V DC AI factory design for the Vera Rubin era Nvidia and Cisco announced the Ultra-Dense Small Form Factor Pluggable (USFP) standard, the industry’s first module for 400Gb/s-based networking fabrics Nvidia and Google announced Falcon Transport support on future Nvidia ConnectX-10 SuperNICs and BlueField DPUs Before a packed audience, Ian Buck, vice president of hyperscale and high-performance computing at Nvidia, discussed how open infrastructure is becoming a critical ingredient for scaling AI factories worldwide. The news at OCP spotlights how Nvidia’s extreme codesign combined with open standards is accelerating deployment, improving power efficiency and driving tokens-per-watt performance. Vera Rubin AI Factories Advance With MGX Rack Contributions Nvidia joined industry leaders in contributing to the third-generation MGX AI data center reference design through OCP’s Open DC Initiative. Combined with open liquid-cooling technologies such as MQD and MQDB, the effort helps turn proven AI factory designs into industry standards that others can adopt, manufacture and scale. For Nvidia Vera Rubin AI factories, the updated MGX 1.2 specification extends the open architecture for AI factories with rack-scale blind-mate liquid cooling, interoperable rack-scale interconnect infrastructure and a liquid-cooled 5,000A busbar designed for higher-power AI systems. It also adds native 19-inch equipment support and higher-density rack designs. MGX 1.2 further expands modularity with configurable I/O bays, fanless liquid-cooled compute trays, standardized power and cooling interfaces, and a common infrastructure that helps ecosystem partners build interoperable accelerated computing platforms. It improves assembly, test and service times to streamline manufacturing and field service to enable faster and more efficient infrastructure buildout. The architecture supports rack deployments up to 250kW while simplifying serviceability, deployment and infrastructure reuse. The Vera CPU rack design specification extends the Nvidia MGX open architecture beyond accelerated computing, providing a purpose-built platform for the growing agentic AI era. While Vera Rubin NVL72 serves as the foundation for large-scale training and inference, the Nvidia Vera CPU rack is designed to support tool calling, orchestration and sandboxed execution, helping AI agents interact with applications, data and services in real time. Built on the third-generation Nvidia MGX rack architecture, the Vera CPU rack shares the same rack-scale design principles that unite compute, networking, power and cooling into a common modular platform. This approach enables partners to deploy specialized infrastructure while benefiting from a shared ecosystem, simplified integration and a consistent foundation for next-generation AI factories. Nvidia Launches New Open Source Software Components for DSX AI Factory Nvidia DSX AI factory platform applies extreme codesign to unify computing, networking, power, cooling, facilities and software, helping AI factories operate as a single optimized system, maximizing AI output within available infrastructure constraints. At the center of this unified system is DSX OS, the open operating layer that turns the DSX architecture into coordinated, repeatable operations at scale. At OCP, Nvidia expanded DSX OS with open source components for configuring networks, validating clusters, managing racks and provisioning bare metal: Nvidia Config Manager: Automates switch configurations at scale, allowing customers to deploy, validate and maintain consistent AI factory network fabrics with minimal to zero manual intervention Nvidia Cluster Readiness Engine: Helps eliminate costly job crashes by stress-testing GPU clusters with real workload simulations to guarantee hardware health before training begins Nvidia Rack Management Service: Offers a rack hardware abstraction and operations solutions that treats racks as first-class units for improved AI factory scale firmware management Cluster API Provider for Nvidia Infrastructure Controller: Accelerates bare-metal deployment and tenant onboarding, turning raw AI hardware into production-ready clusters in hours instead of days Developed from Nvidia’s experience running Nvidia DGX Cloud, these open source components enable cloud providers and software partners to integrate AI factory capabilities directly into their multi-tenant platforms. Nvidia and Hyperscalers Publish Open Standards for Next-Generation AI Factories For AI infrastructure to scale globally, it needs more than advanced hardware — it needs a common foundation that the entire industry can build on. At OCP, Nvidia joined AMD, Google and Meta to publish a new open specification that establishes that foundation. The Open Data Center Specification v0.7 defines a unified blueprint for next-generation AI factory facility design — from power architecture to cooling infrastructure to physical layout. The OCP Grid Resilience Specification, published by Google, Meta, Microsoft and Nvidia, establishes how large-scale AI infrastructure should behave during utility grid disturbances: staying connected, responding automatically and restoring to near-full load within less than two seconds. With these standards now open, manufacturers around the world have a common target to build for. Equipment makers, colocation providers and data center operators can begin designing, fabricating and delivering the infrastructure layer that powers AI factories under construction globally — without waiting for proprietary specifications from individual customers. Being Nvidia DSX reference design-compatible, these specifications provide a validated, deployable implementation of both specs, from facility layout and power architecture to the software that monitors and responds to grid signals in real time. For operators building Vera Rubin AI factories, there’s now a straight line from open community standard to a running system. Visionbay.ai Designs 800VDC AI Factory for the Vera Rubin Era As AI factories grow larger and more powerful, one challenge looms over them all: delivering enough power to the accelerated computing systems driving the next generation of AI. At OCP, Visionbay unveiled plans for K-1, a next-generation AI factory platform designed around an 800 VDC architecture and built with future Nvidia Vera Rubin deployments in mind. The project combines Nvidia’s 800 VDC reference architecture with power and thermal technologies from Vertiv to create a scalable foundation for high-density AI infrastructure. The design addresses a growing industry challenge. As AI training, inference and reasoning workloads expand, rack power densities continue to rise. Traditional low-voltage power distribution becomes increasingly difficult to scale, requiring more copper, more cabling and more power-conversion equipment. By adopting Nvidia’s 800 VDC architecture, K-1 creates a path toward higher-density AI infrastructure while preserving flexibility for existing deployments. Rather than requiring a complete transition on day one, the platform is designed to phase in 800 VDC distribution where it delivers the greatest benefit, helping operators prepare for future generations of accelerated computing without extensive facility redesign. The architecture is designed around cluster-level power centers that centralize AC-to-DC conversion and distribute 800 VDC closer to compute resources. The approach simplifies downstream power delivery, supports modular expansion and creates repeatable building blocks for future AI factory growth. K-1 also reflects the system-level design philosophy behind Nvidia AI factories, where power, cooling and computing are engineered together. With support for liquid-cooled infrastructure, scalable power distribution and future Vera Rubin-class deployments, the project demonstrates how ecosystem partners are translating Nvidia’s AI factory architecture into deployable infrastructure designed for the next era of accelerated computing. Meta and Nvidia Advance AI Networking With Spectrum-6 and Multiplane Technology At the event, Meta and Nvidia announced that Meta is adopting Nvidia Spectrum-6 102.4Tb/s Ethernet switches to build larger, higher-performance Nvidia Vera Rubin AI factories on open networking. Spectrum-6 delivers twice the switching capacity and per-lane bandwidth of Spectrum-4, and provides a lossless Ethernet AI fabric at 200G per lane, with high effective bandwidth and performance isolation that keeps one job’s traffic from slowing another’s. Meta’s Spectrum-6-based switch, N-IceCube, slots into IcePa
Summary: Integrated Open Compute Project (OCP) based portfolio spans rack-scale AI/HPC systems, ORv3 and ORW racks, 48V DC power, networking, and liquid cooling solutions to enable higher-density compute in existing and new data centers Portfolio extends from infrastructure to intelligent operations with DCBBS Coolants, in-rack CDUs, switches, and Supermicro System Management Software Suite for infrastructure management Supermicro DCBBS brings these OCP-based technologies together into integrated rack-scale solutions, simplifying and speeding deployment across compute, power, networking, and cooling for a faster Time-to-Online (TTO) Super Micro Computer, Inc., an AI, enterprise, storage, and 5G/edge total IT solution provider featuring Data Center Building Block Solutions (DCBBS), announced an expanded portfolio of Open Compute Project Accepted systems, racks, and rear door heat exchangers (RDHx). Supported by DCBBS, the solutions portfolio can be incorporated into complete end-to-end rack- and cluster-scale deployments.“The AI boom is redefining how data centers are designed, built, and deployed, and Supermicro is leading this transformation with DCBBS,” said Charles Liang, president and CEO, Supermicro. “By integrating compute, networking, power, advanced cooling, software, and services into validated rack-scale solutions, we help customers simplify complexity and accelerate the path from innovation to production. DCBBS enables customers to reduce T and TTO by delivering essential AI infrastructure faster and more efficiently.” By leveraging OCP community best practices and DCBBS design and services, data center operators can increase compute density and energy efficiency for AI and HPC workloads based on an open and validated rack-scale foundation – from systems and busbar to rack-level and data center cooling – to bring high density solutions online more efficiently to accelerate Time-to-Market (T) and TTO. “Customers need open, flexible infrastructure that can scale with the rapidly evolving demands of AI while fitting the realities of their data centers,” said Dirk Van Slyke, VP, marketing, OCP. “By bringing OCP-accepted systems, racks, power and cooling together in validated rack-scale solutions, Supermicro is helping customers simplify integration, maximize facility capacity and efficiency, and accelerate the deployment of production AI infrastructure.” The ORv3 and ORW racks replace per-server power supplies and cables with a centralized 48V DC busbar, allowing customers to optimize their CPU and GPU systems for higher density compute racks. This density is further supported by Supermicro’s DLC-2 Direct-to-Chip liquid cooling, which removes heat more efficiently from CPUs, GPUs, and other critical components, while residual heat can be removed from the rack by purpose-built ORv3 RDHx’s without requiring additional retrofit of data hall air conditioning systems. Supermicro RDHx units can be mounted to the rear of ORv3 and ORW racks and remove residual heat from server exhaust before it enters the data hall. The portfolio spans 10 kW to 120 kW of cooling capacity, giving operators a practical way to increase rack density in both new AI facilities and existing data centers. DC-powered models connect to the rack’s busbar to reduce cabling, while designs include N+1 redundant fans to ensure uptime and a smart anti-condensation system to prevent moisture damage to other components inside the rack. Operators can monitor and manage the entire portfolio of DCBBS components, through SuperCloud Composer using industry-standard protocols. Further, Supermicro’s software, such as SuperCloud Director, SuperCloud Automation Assistant, and SuperCloud Developer Console, enables organizations to manage and operationalize all aspects of modern AI factories, enterprise data centers, and NeoCloud infrastructure, through a unified software control solution. As part of DCBBS portfolio, Supermicro also delivers a comprehensive portfolio of AI networking solutions, ranging from air and liquid-cooled 800G and 1.6T Ethernet switches including next-gen Co-Packaged Optics (CPO) platforms built on Broadcom Tomahawk 6 switching silicon, optimized for EIA or ORv3 racks. The Supermicro Enterprise Advanced SONiC Networking OS gives customers the flexibility to select the networking architecture that best meets their performance, power, scalability, and deployment requirements as AI and large-scale data center environments continue to evolve. Supermicro DCBBS will also include Nvidia Spectrum-X Ethernet Photonics switch systems, the first co-packaged Ethernet switches with 200Gb/s SerDes. Built on the 102.4 Tb/s Nvidia Spectrum-6 Ethernet ASIC, Spectrum-X Ethernet Photonics delivers 5x better power efficiency, 10x greater MTBI, 5x longer uptime for AI applications and 1.3x faster time to deployment, compared to pluggable transceiver-based networks. Spectrum-X Ethernet Photonics is in production now. These include: 1 OU FlexTwin Solution: A purpose-built rack-scale HPC solution featuring 1 OU 2-node systems powered by the latest Intel Xeon 6 or AMD EPYC CPUs Nvidia Vera Rubin NVL72: Supermicro’s OCP contributed Nvidia MGX 1.2 Rack Series is engineered exclusively for Nvidia Vera Rubin NVL72 and Nvidia Vera CPU platforms with Supermicro’s DCBBS DLC-2 liquid-cooling stack support to streamline rack integration to accelerate deployment 2 OU Nvidia HGX B300: Built to the OCP ORv3 specification with advanced liquid cooling technology, each compact 8-GPU node fits into 21-inch racks, enabling up to 18 nodes and 144 total GPUs per rack 2 OU 4-Node Rack-Scale Solution: Optimized architectures unlocking breakthrough performance, efficiency, and rack density for 24/7 agentic AI, featuring up to 45,696 Arm AGI CPUs per rack 250 kW 4U In-Rack CDU: Features a high cooling capacity and a compact design with up to 250 kW cooling capacity in a compact 4U form factor. It supports high-density AI racks with 45°C warm-water cooling and energy-efficient data center operation OCP ORv3 Rack Series: 44OU and 48OU 21-inch racks with integrated busbars and a 5,000 lb. (2,268 kg) certified static load capacity, liquid cooling ready architecture, optimized mechanical design, including MGX 1.2 (Gen 3) racks AMD Helios Platform Solution: ORW architecture that is fully integrated and purpose-built for high-volume inference, frontier-model training, fine-tuning, as well as sovereign and agentic AI ORv3/ Chiller Door: Compatible with ORv3 rack and features 20-100 kW cooling capacity, and Redfish/SNMP/WebUI/Modus control ORW Chiller Door: Compatible with ORW rack and features 60 kW cooling capacity and Redfish/SNMP/WebUI/Modus control DCBBS Coolants: Built for an OCP-Style liquid-cooling stack customers have two ready-to-use PG coolants for the TCS loop – DLC-1 for standard liquid-cooled racks, and ultra-low-conductivity DLC-2 for specialty cold-plate designs. Both are designed to align/compatible with the OCP PG25 Base Spec, so racks, in-rack CDUs, RDHx, and cold plates can run as one cooling stack Rear Door Heat Exchanger (RDHx): Six rack-mounted cooling solutions that remove heat from liquid-cooled racks. Cooling capacities range from 10 kW to 120 kW, with AC and DC power options available Power shelves (1 OU) and Battery Backup Units (2 OU) easily fit into OCP racks 2 OU CPO Switch: Designed for OCP ORv3 racks with 40-60 VDC busbar power and blind-mate QD08 liquid cooling. Delivers 102.4 Tbps across 128 × 800G ports with Supermicro Enterprise Advanced SONiC support System Management Software: Supports Redfish APIs and OpenBMC based architecture for remote management. Availability of attestation and PQC algorithms for security compliance with OCP standards DCBBS is Supermicro’s integrated approach to building and deploying production-ready AI infrastructure-from rack-scale systems to complete AI factories. DCBBS brings together accelerated compute, high-performance networking, storage, power, advanced liquid cooling, system management software, and deployment services in validated solutions, optimized for, and co-designed by, each customer. By combining Supermicro’s engineering and manufacturing capabilities with leading technology ecosystems, DCBBS helps organizations reduce deployment complexity and total cost of ownership, while optimizing performance and efficiency.
Designing Edge AI for Real-Time Systems
TI unveils 3-GSPS ADC for AI Data Centers at OCP
2026 Cisco AI Infrastructure OCP Pre-Briefing Final Slide 10: Cisco and NVIDIA USFP 400G optics Ahead of the OCP Global Summit, Cisco briefed analysts on AI-infrastructure announcements spanning optics, silicon, systems, and software. For us, the headline is clearly the ultra-dense small form factor, or USFP, a pluggable module Cisco developed with NVIDIA for 400G SerDes lanes, which it says enabling higher-density 1.6Tbps fabrics. Cisco also detailed the Silicon One G300 in first systems, a G302 front-end top-of-rack switch coming in Q4 2026, and the Silicon One A100L aimed at lower-cost 10G/1G out-of-band management switches. USFP will be a big one with both Cisco and NVIDIA behind it and because next-generation pluggable optics are a key part of the 1.6Tbps Ethernet generation. To me, the A100L stood out on the briefing call since Cisco’s custom silicon applied to cost-sensitive switching rather than only the high-performance fabric. Cisco OCP AI Networking Announcements Cisco and NVIDIA are designing a new pluggable form factor for 400G SerDes lanes rather than today’s common 200G lanes. We will say “common” because there is still a lot of 56G PAM4 SerDes and 112G gear being sold today. Moving to 400G means 1.6Tbps networking can happen on four lanes, scaling to 6.4T aggregate across 16 lanes and 12.8T across 32. Cisco and NVIDIA are jointly drafting the multi-source specification so other vendors can build to it. 2026 Cisco AI Infrastructure OCP Pre-Briefing Final Slide 10: Cisco and NVIDIA USFP 400G optics It is interesting that QSFP/ OSFP were not sufficient for the next-gen speeds. Pairing that optics work with switch silicon produces the ethernet-to-optical architecture on the next figure, which places the Silicon One G300 in first-shipped Cisco 8000 and N9000 systems at 102.4T of capacity across 1.6T ports. Now, the new G302 drives a 51.2T front-end top-of-rack switch using 200G SerDes. 2026 Cisco AI Infrastructure OCP Pre-Briefing Final Slide 11: Cisco AI Ethernet and optical architecture The Silcon One A100L made me ask a question at the analyst pre-brief. Custom AI silicon usually appears in high-performance fabric switches since that is where the value from doing something custom often can be captured. Lower-end silicon found in management boxes running the 1G/10G networks in racks tends to be mostly just a volume play. Cisco said it was proof the architecture scales and hyperscale clients wanted to run SONiC on everything. I asked what the licensing model would be, more perpetual like a C1300 or more like the Nexus 9K series but did not get a clear answer on that one so I am going to call it a TBD. The reason I asked is that if you are doing custom silicon versus like a Marvell Prestera and not capturing software revenue, that feels like a tough road to take. Live Protect for Cisco SONiC on Nexus One adds runtime vulnerability shielding to N9000 switches, applying policy to a running system so operators can protect it before scheduling a conventional patch and reboot. Cisco SONiC is set to be available in 2027, but that feels like a big move for Cisco as well. 2026 Cisco AI Infrastructure OCP Pre-Briefing Final Slide 23: Cisco Live Protect for SONiC Cisco positions Live Protect to shrink the exploit window, with availability slated for Q2 2027 in Cisco-validated SONiC environments. Customers will also be able to choose between community or custom SONiC and a Cisco-validated distribution, as the final operating-model figure shows. 2026 Cisco AI Infrastructure OCP Pre-Briefing Final Slide 24: Cisco SONiC operating model options Rounding out the software story is how Cisco intends customers to run SONiC. An operating-model figure lays out two tracks. A community or custom path offers full customization and source access for maximum control, while a turnkey Cisco-validated path provides a defined upgrade path and professional services. Notably, Cisco’s use of NVIDIA Spectrum-X is an option we have covered before, but aside from supporting the open-source SONiC, Cisco is also supporting switching platforms from NVIDIA. Final Words With Cisco and NVIDIA behind USFP, it will become an industry standard. Hopefully we will get to see some module shells on the OCP show floor this week. Silicon One G302 is a meaningful milestone on its own, but A100L sliding into out-of-band management feels almost crazy to me, since the sub-1Tbps switch space was widely assumed to be largely commoditized.
Marvell Introduces Six-Channel CXL 3.2 Memory Expanders
Intel-GPU-D-Series-Accelerator Hero Amid a flurry of product announcements and updates at this year’s Open Compute Project Global Summit, Intel is at the show to deliver an update on Crescent Island, the company’s forthcoming AI inference GPU. After outlining the chip’s architecture back at Hot Chips 2026, the company is offering a short update on the product today, outlining some of the chip’s final performance specifications along with giving the cards based on it a proper name. Going forward, Crescent Island will be sold as part of Intel’s GPU D-Series. Hot Chips 2026 Intel Crescent Island Slide 19 LPDDR 5x Open Speeds and Feeds: Crescent Island Nears Release As a brief refresher, Crescent Intel’s is first commercial AI-focused data center GPU since Ponte Vecchio in 2021. With two of Ponte’s successors canceled over the last few years – Rialto Bridge in 2023 and then Falcon Shores in 2025 – Intel announced Crescent Island at least year’s OCP Global Summit as an interim product to target the AI inference market with a heavily cost and power-optimized part. The resulting chip is not meant to be on the same performance level as flagship chips such as NVIDIA’s Blackwell Ultra or AMD’s MI455X, but then it will be a lot smaller and cheaper as well. Most recently, Intel delivered an update on Crescent Island back in August, where the company offered a fairly detailed look at the architecture behind the chip. Based on an enhanced version of their Xe3 GPU architecture that they are calling Xe3P, Crescent Island heavily fortifies the architecture with a far larger number of XMX matrix engines, and a far larger LPDDR5X memory subsystem to keep those matrix blocks fed. In effect, Intel is banking on a massive matrix math version of Xe3 that is backed by a large LPDDR5X memory pool of up to 480GB being able to compete favorably with other inference accelerators on the market today. Hot Chips 2026 Intel Crescent Island Slide 8 Crescent Island Architecture For this year’s OCP Global Summit, in turn, Intel is finally publicly locking down some of the specifications for the forthcoming accelerator. In particular, we finally have the theoretical total compute and total memory bandwidth figures for the first card based on Crescent Island, which gives us enough information to paint a fairly detailed look at how the chip is configured. Intel GPU D-Series Specifications Intel GPU D270 Xe Cores 32 XMX Engines 256 GPU Clockspeed ~2.5GHz Peak Matrix Throughput (FP8) 1.3 PFLOPS Peak Vector Throughput (FP64) 10.2 TFLOPS Memory (Max) 480GB LPDDR5X (ODMs) 160GB LPDDR5X (Intel) Memory Bandwidth 1.5TB/sec (~9375Mbps x 1280-bits) ECC Yes L2 Cache 32MB I/O PCIe Gen5 x16 TDP 350W Form Factor PCIe CEM (Air Cooled) Architecture Xe3P GPU Crescent Island In regards to performance, Intel is touting 1.3 PFLOPs of FP8 matrix performance. With 256 XMX matrix engines on the chip itself, this gives us a clockspeed of roughly 2.5GHz. As for memory bandwidth, the flagship card will offer 1.5TB/second of memory bandwidth, which comes courtesy of its hefty 20 chip, 80 channel LPDDR5X memory bus, with the memory clocked at roughly 9375MT/second. While Intel had previously discussed the architecture of the chip, the total performance and bandwidth had been up in the air. In practice, these figures are very close to what most of the industry has been expecting for the accelerator given current LPDDR5X memory speeds as well as the kind of clockspeeds that similar accelerator architectures have been hitting. In that respect Intel is delivering right in the neighborhood of where they should be – meaning that Crescent Island is not surpassing expectations, but it is not failing to meet them, either. As to whether 1.3 PFLOPs of FP8 will be sufficient for Intel’s target market of data center inference operations, that remains to be seen. For comparison’s sake, AMD’s similar PCIe CEM form factor MI350P accelerator can offer a theoretical peak of 2.3 PFLOPs of dense FP8 matrix math; so a Crescent Island card comes in some 40% lower. With that said, comparing different architectures based on theoretical throughput alone rarely pans out in the real world, so a lot of the GPU’s competitiveness is going to hinge on its overall architectural efficiency compared to AMD’s CDNA 4 architecture. Especially if Intel can do meaningfully better in prefill, which is traditionally where GPU-based architectures bottleneck in data center-scale workloads. Hot Chips 2026 Intel Crescent Island Slide 3 Accelerator Portfolio for Agentic AI The bigger differentiator there will likely be power and cooling. The flagship Crescent Island card is a 350 Watt card that can be air cooled, whereas MI350P’s highest performance configuration is 600 Watts. Even more so than inference performance, Intel has been touting Crescent Island’s efficiency on a performance-per-watt basis, so for Intel’s intended market the card does not necessarily need to be the fastest option, so long as it is a more power efficient option than other PCIe cards. Finally, Intel has once again confirmed that we will see multiple memory configurations with Crescent Island cards. The company’s own card will ship with 160GB of LPDDR5X memory (20x8GB chips). However, ODM partners will be able to offer versions with up to 480GB of memory, an extreme amount of memory enabled by 24GB LPDDR5X chips and a far larger capacity than any other PCIe form factor accelerator announced thus far. Intel GPU D-Series: Crescent Island Gets a Name Meanwhile, Crescent Island cards are finally getting a series name. For Intel’s new series of data center AI inference cards the company is launching a new brand name for them: the Intel GPU D-Series. Intel-GPU-D-Series-Accelerator-Render The first (and so far, only) card in the series is the GPU D270, pictured above. The image, a render, does not reveal anything we do not already know about Intel’s target market for the cards. But it does reinforce that this is a double-wide PCIe card meant to go into traditional PCIe-based data center servers. Notably, Intel is not keeping the Data Center GPU Max (or Flex) branding here, which is what Intel has used for its Ponte Vecchio and Arctic Sound-based PCIe cards. Despite being aimed at much of the same HPC market as the Data Center GPU Max family (and effectively its successor), the GPU D-series is its own product through and through. The D-series suffix does invite some comparisons to another Intel D-named product, the Xeon D lineup. However, those chips were aimed at networking and edge devices, whereas the 350 Watt GPU D270 is very much a data center part. Plus the Xeon D brand was effectively put on a retirement glide path in 2025 with the launch of the Xeon 6 SoC series of chips (Granite Rapids-D), which are replacing Xeon D in that market. So the best way to interpret the new name is that Intel is starting anew, at least as far as GPU hardware goes. Final Words Wrapping things up, with today’s announcement Intel is slowly laying the remaining groundwork for the full launch of the GPU D-series. At this point the company has all but fully revealed its specifications and theoretical performance – now it is just a matter of when it will ship, and how much Intel will charge for it. But the answers to those questions will have to wait for another day. For now, Intel is confirming that they are sampling cards to customers. However the company has not yet announced a launch date for the cards, or even confirmed that they will launch in what remains of this year. So AI server vendors looking for an alternative for PCIe inference cards will have to look towards 2027 for the release of Intel’s GPU D-series.
Designing AI Data Center Fabrics with PCIe 6.0 High-Radix Switches
AMD EPYC 8635P 1 A few months back AMD launched their EPYC 8005 “Sorano” family of server chips. The mainstream server counterpart to AMD’s high-end EPYC 9005 chips, Sorano filled a significant hole in AMD’s chip lineup by bringing their Zen 5 architecture to a more modest server platform. As we noted in our review at the time of the launch, Sorano has become a rather significant offering for AMD not only because of the market it fills, but because of just how much it has improved over its own predecessor, the Zen 4-based EPYC 8004 Siena. With a larger number of cores, far higher clockspeeds, and support for much faster DDR5 memory, Sorano made AMD’s SP6 platform a far more capable and competitive offering in the market. AMD-EPYC-8005-Server-CPU-At-A-Glance A consequence of that, however, is that almost everything that customers knew about the 8000 series went out the window; despite using the same socket, the Sorano chip family is significantly different in terms of everything from performance and price to the number of individual SKUs within the chip stack. So what are the highlights among the EPYC 8005 family, and what chips should customers go with? To answer that, here is ServeTheHome’s look at the EPYC 8005 product stack, outlining what some of the best options for different scenarios/optimization points. AMD EPYC 8005 SKU List and Value Analysis First up, here is the complete list of EPYC 8005 chip SKUs. AMD-EPYC-8005-Server-CPU-SKUs For their first generation of 8000 series parts, the EPYC 8004 Siena, AMD kept things relatively simple with a modest product stack and consistent features among all of the chips, and that is once again the case for Sorano. The mid-tier, single-socket server platform does not gate any features behind specific SKUs, and as a result every chip from the entry-level 8 core 8025P to the top-end 8635P gets access to same set of features. This includes 6 channels of DDR5 memory support (including 2DPC support), 96 PCIe Gen5 lanes, and, of course, AMD’s Zen 5 CPU architecture. With Sorano being a notable step up here since these are AMD’s higher-clocking full-size Zen 5 cores, and not the compact cores used in Siena. For potential customers, this simplifies the calculus behind picking which chip to go with by quite a bit. The only real decisions to be made are around core counts, power consumption, and all of the second-order effects thereof. Drop-in upgrades are even a viable option here since AMD is using the same SP6 socket as with the EPYC 8004 generation – though as we have seen, some vendors are releasing new motherboards for Sorano anyhow. ASRock Rack SORANOD8-2L2T-Motherboard (Rear) Even with just 7 chip SKUs, however, the spread between them in core count, clockspeeds, and power consumption are significant. The SP6 IOD can be connected to up to 12 Zen 5 CCDs, so AMD has run the gamut here, with between 8 and 84 CPU cores. This means that while they all share the same platform and architecture, the resulting performance of these chips can be quite different depending on the workload. All of which makes understanding and profiling a target workload all the more important in choosing a chip. One important factor is going to be how well a workload scales up over multiple cores, versus requiring faster individual cores to hit its best performance. Every single chip SKU has a maximum single core turbo clockspeed of 4.5GHz (a significant improvement from EPYC 8004), so very lightly threaded workloads have a lot of headroom. But, generally speaking, one is not buying an EPYC CPU just to run a couple of threads. Rather, there is some major scale needed here in terms of core counts, I/O lanes, memory bandwidth – or possibly all three. AMD EPYC 8005 SKU Analysis – All-Core Boost Frequency Taking a look at all-core turbo clockspeeds, we see that clockspeeds here are almost, but not entirely, inverted with core counts. The 84 core EPYC 8635P offers an all-core turbo boost speed of just 3.45GHz, while the 24 core 8225P hit 4.1GHz, and the smallest 8025P can go higher still. The outlier that breaks this pattern is the 16 core 8125P, which despite having fewer cores than the 8225P actually has a lower all core turbo clockspeed. Outside of the 8125P, no single chip here is quite the sweet spot for per-core performance. But the middle-child 8325P has the strongest claim. AMD EPYC 8005 SKU Analysis – TDP per Core Shifting over to power consumption, AMD’s default TDPs are directly proportional to the core counts, even with the lower core chips offering higher average clockspeeds. For “performance at all costs” there is the 8635P with its 84 cores and 225 Watt TDP. With 20 more cores than the next-fastest chip it is the clear winner in terms of throughput. And, somewhat surprisingly, it is a lot more power efficient than the next chip down as well; the cost of going from a 64 core chip to an 84 core chip is just 15 Watts at default TDPs. AMD’s default TDPs vary from chip to chip, but in general the higher-end Sorano chips are all relatively close to each other in TDP at around 200 Watts – thanks in part to those higher clockspeeds we talked about earlier. This also means that there is a clear and consistent progression from one part to the next in regards to how much power is needed per core – and really, the overall energy efficiency of the chip. The top-end 8635P ends up being the most efficient, at just 2.7 Watts per CPU core. This rises to a bit over 4.1W with the 48 core part, and finally to nearly 12W per core with the 8 core 8025P. With the entire EPYC 8005 family sharing the same IOD with the same memory and PCIe support, this is a classic case of where the power costs of the uncore (or IOD, in this case) are getting amortized over fewer and fewer CPU cores as the overall core counts drop down. AMD EPYC 8005 SKU Analysis – L3 Cache per Core The flip side to that general decline in per-core energy efficiency is that fewer cores to amortize the impact of the IOD also means that there are fewer cores sharing/competing for other uncore resources, which can be beneficial in other ways. A prime example is the amount of L3 cache per core, which generally increases as the CPU core counts decrease. This is chiefly due to how AMD goes about building these SKUs and the number of CCDs they use, with most SKUs utilizing CCDs with multiple disabled cores – leaving more cache for the rest of the cores. With 384MB of L3 cache, the top-end 8635P is, of course, the most cache-filled chip. But with so many cores, it also works out to be tighter on cache per core than most, at just under 4.6MB per core. Though it is the 64 core 8535P that is actually the most cache-contested chip here, at just 4MB per core thanks to AMD using 8 fully-enabled CCDs. Fittingly, the smaller core count chips have the most cache per core overall; the 8435P and 8225P both have 5.3MB per core, while the remaining three SKUs all get a spacious 8MB of cache per core. Especially with AMD not producing 3D V-Cache server part in this generation, this makes the 8325P and its ilk one of the best options for highly-threaded workloads that strongly benefit from additional L3 cache. AMD EPYC 8005 SKU Analysis – Memory Bandwidth per Core As for overall memory bandwidth, with all seven 8005 chip SKUs sharing the same 6 channel DDR5-6400 memory controller, the amount of memory bandwidth on the SP6 platform is fixed. Or to put it another way, the amount of bandwidth per core is directly (and inversely) proportional to the core count. With 307GB/second of memory bandwidth overall for the platform, the 8 cores on the 8025P get an ample 38GB/second each; while at the top end the 8635P reduces that to just 3.7GB/second per core. Finally, how does all of this look with pricing taken into account? AMD EPYC 8005 SKU Analysis – List Price Against Cores As AMD’s more budget-friendly server platform, SP6 and Serano is fairly cheap as far as server chips go. In practice, almost all server builds are going to spend more on RAM to fill the server than they will the CPU itself. With the caveat that nearly no one pays AMD’s list prices for their server CPUs, AMD’s chip pricing is somewhat variable; lower SKUs are always cheaper, but they do not scale consistently with price. Which means the price-per-core bobs up and down from one SKU to the next. AMD EPYC 8005 SKU Analysis – Price per Core The best value here is found in the 16 and 24 core SKUs, which at list price are under $50 per core. In relative figures, it is actually a pretty significant improvement over the other SKUs, which are $60+ per. Understandably, the 8 core SKU does not fare especially well here at $66 per core. Otherwise, the top-end 84 core SKU is actually decent for being a top chip, at $69 per core. The weakest SKU, interestingly enough, is the 64 core SKU, which is priced only a few hundred dollars less than the top-end chip, yet drops 20 cores in the process. As a result, it works out to being $86 per core – a significantly higher price than any of the other SKUs. Final Words As AMD’s more economical server platform, the EPYC 8005 Sorano family fills an important role in the company’s server lineup. With more than a few customers in need of a literally smaller chip family that can still bring the full advantage of the Zen 5 feature set but without quite so many CPU cores or expensive memory channels, the EPYC 8005 family fills that role well. And with AMD keeping the chip stack relatively simple at just 7 SKUs and without any major feature differentiators, it keeps the overall chip calculus for customers reasonably straightforward. For pure compute throughput, the EPYC 8005 stack is rather clear-cut. The 8635P is easily the fastest chip in terms of total (on paper) compute throughput thanks to its 84 CPU cores, as well as looking very good in terms of power efficiency. The trade-off there is that clockspeeds are not all that high compared to other SKUs, and it has some of the highest
SPECviewperf CATIA ThreeLoftJetsDarkMirror A couple of weeks back, the Standard Performance Evaluation Corporation released a new Linux version of SPECviewperf, the consortium’s workstation graphics benchmark. Now up to version 15.0.1 and the group’s first Linux Edition release in almost half a decade, the new release gives the Linux graphics benchmark a significant facelift in both the features it offers and the workloads it tests. Despite the long gap between Linux Edition releases, the timing of this new release could not be better. Beyond a slew of updates to the venerable Linux graphics benchmarking suite, including workload updates and a whole new GUI, the latest version of SPECviewperf adds Arm AArch64 support, marking the first time the graphics benchmark has been natively available on any Arm-based system. Consequently, the Linux version of the benchmark is treading new ground for SPECviewperf, something it rarely gets to do, giving us valuable first-look insights into how well Arm devices can handle traditional workstation graphics workloads. We, of course, could not help ourselves and decided to take some time looking at the newest Linux benchmark and how it runs on some of our most recent Arm-based boxes. So, without further ado, let us jump right in. SPECviewperf 15.0.1 Linux Edition Highlights SPEC has offered a Linux version of its workstation graphics benchmark suite for nearly a decade, first releasing a Linux build in 2019 with SPECviewperf 13. Because many CAD, CAM, and 3D rendering workstation applications are OpenGL-based (or not available on Linux at all), the consortium has ported its graphics workloads to Linux to provide a counterpart to the Windows version. The net result is that the Linux version supports a smaller set of workloads overall (there is no DirectX here, for a start), but it still offers a solid look at workstation performance on Linux. All told, the Linux Edition of SPECviewperf 15.0.1 offers 8 of the Windows suite’s 11 benchmarks, including graphics traces from Blender 3.6, 3DEXPERIENCE CATIA/CATIA V5, Creo 9, Maya 2025, Solidworks 2024, NX 2406, and visualizations from OpendTect and the Tuvok library. Compared with the previous version of the suite, 2020 3.0, the Blender workload is new, while CATIA, Creo, Maya, Solidworks, and NX workloads have all been updated, as they were in the Windows version released last year. SPECviewperf Blender MetroverseColorXray-scaled result Notably, this year’s release of the benchmark suite also gets a newer GUI with more features, bringing more graphical controls and an improved setup routine to the workstation graphics benchmark. SPECviewperf 15.0.1 Linux Edition GUI That new GUI goes hand-in-hand with the ability to download and install just a fraction of the benchmark suite’s workloads, which, when fully installed, take up nearly 100GB of space. SPEC calls this their “snap-in” architecture, which makes each workload a snap-in element of the suite rather than one monolithic suite. It also lets system vendors and other operators more easily test only the graphics workload(s) they care about. SPECviewperf 15.0.1 Linux Edition Workload Installation But arguably the marquee feature is support for AArch64 systems, marking the first time SPECviewperf has been natively available for an Arm-based architecture. The fundamental concept of replying OpenGL traces remains unchanged, as SPECviewperf is a graphics benchmark rather than a full-scope application benchmark, but that playback system can now operate under AArch64 and help to expose how well the graphics hardware and associated graphics drivers perform under Linux. Speaking of hardware and drivers, the Linux benchmark suite supports a narrower range than Windows. While the Linux version of SPECviewperf 15.0.1 can run on any system with an OpenGL 4.5-compliant GPU, in practice it supports only AMD and NVIDIA GPUs, leaving Intel as the odd one out. On the plus side, it supports integrated GPUs, which is extremely helpful for testing the companies’ recent high-performance SoCs, including AMD’s Strix Halo and NVIDIA’s GB10. SPECviewperf 15.0.1 Linux Edition Performance With SPEC’s latest Linux graphics benchmark in hand, we wasted no time loading it on some of our recent Linux systems to look at performance. Getting true apples-to-apples performance here is a bit difficult since few chips/systems fall into identical weight classes, but it is still an interesting look. Specifically, we ran the benchmark on a couple of our Ryzen AI Max+ 395 (Strix Halo boxes), the Dell Pro Max with GB10 (based on the NVIDIA GB10), and, for a high-end workstation, a Threadripper 9980X system with a Radeon AI Pro R9700 installed. SPECviewperf 15.0.1 Linux Edition 4K Performance (All) We will start things with a focus on mini-PCs. Under Linux, we find that performance is heavily in AMD’s favor here. Both Strix Halo boxes are performing far better than the GB10-based box, often by a factor of 2x or more. Our GB10 machines are set up for AI workloads in a cluster, and are Arm-based. At the same time, we would be remiss not to consider how well (or poorly) NVIDIA’s Linux drivers are optimized here, since GB10’s graphics performance under Linux has not been a major focus until now. Take this more as a run just to validate that the Linux suite worked on the platforms, rather than being an ideal benchmark between all of them. Still, for the moment it is a feather in AMD’s cap. Especially for ASRock Industrial’s AI BOX-A395, which remains the fastest Strix Halo box to cross our lab desks. SPECviewperf 15.0.1 Linux Edition AMD 4K Performance Meanwhile, to put those AMD iGPU results in context of what a more powerful discrete desktop system can do, here is a look at their performance plotted next to the results for our Threadripper + Ryzen AI Pro system. It is actually closer than you might first expect: most of the time the Strix Halo systems deliver around half of the performance of the high-end R9700 discrete video card. More surprisingly, they outperformed the discrete card in the NX 2406 workload. So far, the focus on Strix Halo boxes such as AMD’s own Ryzen AI Halo system has been on AI development for obvious reasons, but these benchmarks also show the boxes can be reasonably performant for workstation graphics tasks, as long as the CPU doesn’t become the bottleneck first. Final Words Overall, the release of the Linux Edition of SPECviewperf 15.0.1 comes at an opportune time for the industry, as well as ServeTheHome. As the industry’s de facto benchmark for workstation graphics workloads, SPECviewperf carries an immense amount of weight within the industry. And by refreshing the benchmark suite to not only bring its workloads up to date with its Windows counterparts, but also adding Arm AArch64 support for the first time, this gives everyone a very valuable initial look into the workstation graphics performance of the recent slate of Arm-based mini-PCs that have been hitting the professional market. SPECviewperf Solidworks NASACrawlerShadedEdges result As for ServeTheHome, we have been reviewing new hardware, including GB10-based boxes and AMD’s Radeon AI Pro R9700 video card, so the release of a Linux benchmark suite is well timed for us. Especially as we are fond of testing under Linux for a multitude of reasons. So do not be surprised if you see SPECviewperf pop up in some future reviews as one of our GPU benchmarks.
GMKtec-EVO-X3-AI-Mini-PC-Hero Calling AMD’s Ryzen AI Max+ chips well-received in the mini-PC market is probably an understatement. The high-performance Zen 5 chips have proven particularly adept in this market thanks to a combination of CPU and iGPU performance, plus high memory capacity and bandwidth from LPDDR5X. Especially in this era of AI development, software developers looking to test and run inference locally have been quick to snap up the mini-PCs. VIDEO One result of this popularity is that AMD’s many mini-PC partners have been addressing a market large enough (and with margins big enough) to justify working through multiple generations of mini-PC designs within the Ryzen AI Max family’s lifecycle. A prime example is GMtec, one of the industry’s better-known mini-PC vendors. Last year the company released its first Ryzen AI Max+ box with the EVO-X2, and this year they are back again with a new and very different Ryzen AI Max+ mini-PC design that they are dubbing the EVO-X3. GMKtec EVO-X3 Key Specs (As Configured) Processors AMD Ryzen AI Max+ 395, 16C/32T (5.1GHz) Operating System Windows 11 Pro Memory 128GB LPDDR5X-8000, Soldered Drive Bays 1x M.2 2280 PCIe Gen4 x4 (Lexar NQ790 4TB) 1x M.2 2280 PCIe Gen4 x4 (Empty) GPU Radeon 8060S Graphics (40 CUs) PSU 230W External PSU Form Factor Mini-PC Dimensions 353 x 186 x 41 mm (13.9 x 7.3 x 1.6 in) Weight 2.3kg (5.07 lbs) Wireless Wi-Fi 7 (2×2) + Bluetooth 5.4 (MT7925) Color Gray & Neon Green Ports Front: 1x USB-A 5Gbps, 1x USB-A 480Mbps, 3.5mm Combo Audio Jack Rear: 2x HDMI 2.1, 1x USB-C 40Gbps, 1x USB-A 10Gbps, 1x 2.5GbE LAN (RJ45, RTL8125BG), 1x OCuLink (Gen4 x4) The EVO-X3 stands out in a crowded mini-PC market for a few reasons. First and foremost, the Ryzen AI Max+ 395 SoC at the heart of the system delivers its AI performance and enables it to tap into 128GB of LPDDR5X memory for its iGPU. The second, and far more unique reason is its connectivity. GMKtec has outfitted the system with an OCuLink port, making it a rare Ryzen AI Max system with external PCIe connectivity, and it surpasses even Thunderbolt 4 systems in available bandwidth. Surprisingly, GMKtec is aiming the EVO-X3 at a pretty broad customer base, even pitching the OCuLink port as a gaming feature for use with an eGPU. In practice, though, it is hard to imagine the system being used as anything other than a productivity desktop, especially since GMKtec even preloads the system with AI development software. That is okay, because the Ryzen AI Max platform has proven well suited for that role. If you wanted to find the GMKtec EVO-X3 online, here is an Amazon Affiliate link. GMKtec EVO-X3 External hardware Overview One of the most notable design aspects of the previous iteration, the EVO-X2 mini-PC, was that the system operates upright, a pretty big distinction from the more classic wide-and-low desktop mini-PC form factors. For the EVO-X3, GMKtec seems to have doubled down on this design strategy even more, resulting in a mini-PC that can only be described as a metal monolith. The stange form factor makes more sense once we get inside. GMKtec EVO-X3 AI Mini PC-Front Angled 3 The metal, by the way, is a notable change from the EVO-X2, which notably (and noticeably) featured a plastic chassis. On the other hand, this EVO-X3 is fully metal. The overall monolithic design is even more clearly meant to stand, especially with the (required) base attached. GMKtec EVO-X3 AI Mini PC-Front 1 The tall, slim profile does mean that there is very little to the front of the system, though. For the purposes of our article layout (and your browser window), we have laid the mini-PC flat, which goes to show just how thin the 41mm PC is. Despite packing in a high-performance processor, it is not much thicker than a desktop replacement-class workstation laptop. GMKtec EVO-X3 AI Mini PC-USB 3.2 Type-A Port 1 This view also underscores the limited I/O connectivity on the front of the PC, however. Aside from the 3.5mm combo audio jack, GMKtec has placed only two USB-A ports on the front of the system, and only one is a fast 5Gbps USB 3.x port. The second USB-A port is an even slower USB 2.x port, and there is no front-panel USB Type-C connectivity. The system supports plenty of I/O bandwidth, as we will see, but just not in the front. GMKtec EVO-X3 AI Mini PC-Power Button 1 Meanwhile, towards the other end of the system, we find a rather striking neon green power button sitting within the grey metal chassis. GMKtec EVO-X3 AI Mini PC-Side 4 GMKtec EVO-X3 AI Mini PC-Side 3 Speaking of aesthetics, the EVO-X3’s standing design is not just a style choice for GMKtec. Both the left and right sizes feature significant ventilation. Meanwhile, if there is any doubt about what the primary market is for this system, the “AI workstation” labeling etched into the left side of the case should remove all doubt. GMKtec EVO-X3 AI Mini PC-Rear 1 Shifting to the rear of the system, we find much better ventilation with clearly visible heatsinks. More importantly, this is also where the rest of the system’s I/O lives, including its unusual OCuLink port. GMKtec EVO-X3 AI Mini PC-OCuLink Port 1 Starting there, GMKtec has opted to route four of the Ryzen SoC’s PCIe lanes to an OCuLink port for directly attaching a device to the system. This port can technically connect any device, but the most common use for OCuLink these days is attaching a dock for an external GPU, making it possible to add a high-end video card (or other accelerator) to the system. The OCuLink specification itself tops out at PCIe Gen4 x4 (or ~64Gbps), so it is not comparable to the amount of bandwidth a full-fledged PCIe slot can offer. With the Ryzen AI Max chips offering only 16 PCIe lanes to begin with (all PCIe Gen4), GMKtec can realistically offer only 4 lanes, since they need the other lanes for other features. In any case, the drawback to OCuLink as an external port is the same here as it always was: it is not a hot-plug-capable port. That is why GMKtec has put a very explicit sticker here warning users not to plug (or unplug) an OCuLink cable while the system is operating. On that note, credit to the engineer who had the foresight here to put the OCuLink port to the left of the DC power jack, isolating it from the hotplug-capable USB ports. GMKtec EVO-X3 AI Mini PC-DC Power Input 2 The thin profile of the EVO-X3 means that GMKtec is relying on an external power supply here. At 230 Watts, they technically could have gotten away with a USB-C power supply, but barrel jack units are still a common fixture here. GMKtec EVO-X3 AI Mini PC-HDMI 2.1 Port 1 Next is the system’s sole USB-C port. A native feature of the Ryzen AI Max SoC, this is a full 40Gbps USB4 port that also supports DP Alt Mode to double as a display output for the system. In fact, this is the only way to get DisplayPort video out of the X3, as there is also no dedicated DisplayPort output on the system. Otherwise, given GMKtec’s focus on external I/O bandwidth with the X3, it is somewhat surprising to see that they did not include a second 40Gbps USB-C port, as the Ryzen SoC provides for two ports. To the right, we have the system’s sole dedicated display output: an HDMI 2.1 port. Another native feature of the Ryzen AI Max SoC, there is little reason not to include it here. GMKtec EVO-X3 AI Mini PC-USB 3.2 Type-A Port 4 Moving down the line, we find another USB Type-A port. The second (and final) USB port on the rear of the system is a 10Gbps port. Including the earlier Type-C port, this gives the X3 a total of 4 USB ports, which is serviceable, but it falls short compared to most other Ryzen AI Max mini-PCs that offer a few more ports. In practice, it means the OCuLink port and USB-C port are doing a lot of heavy lifting as far as I/O goes, as there simply are not a lot of ports otherwise for plugging in peripherals after you add a mouse and keyboard. There is again a reason for this that we will see inside. Finally, we have the system’s dedicated Ethernet jack. This is a 2.5GbE port backed by Realtek’s RTL8125BG controller. This is a common enough sight across PCs these days, but for a recently-released Ryzen AI Max system, it is a shame that GMKtec did not use one of Realtek’s newer 10GbE chips, which have become readily available (and relatively cheap) this year. Not including 10GbE is quickly becoming a missed opportunity for AI development-focused PC. GMKtec EVO-X3 AI Mini PC-Rear Angled 1 Shifting perspectives once again, here is a shot of what is on top of the X3 when the system is standing. Matching the colorful neon green accent of the power button we saw earlier, the solid green top gives the system a distinct two-tone color scheme. And perhaps a smidge of irony for the Ryzen-powered system, since it is much closer to NVIDIA’s shade of green than AMD’s. In any case, the top features another airflow vent as well. So, like virtually every other side of the system, it needs to be kept clear for cooling purposes. This also serves as the one significant non-metallic portion of the system for cleanly routing the wireless radio antennas. GMKtec EVO-X3 AI Mini PC-Bottom 1 Last but not least, here is a look at the bottom of the system. Normally hidden by the system’s base, this is where GMKtec has placed the product stickers, as well as the means to access the system’s internals. GMKtec EVO-X3 AI Mini PC-Base Kit 2 Looking at the base itself, interestingly, GMKtec has opted to etch the full system information into the base, including its power specifications and regulatory trademarks. This ensures that the information is visible without dismantling the system, but it means that the base is an integral part of the system for more than just holding up the monolithic mini-PC. The base relies on a pair of screws to secure it to the bottom of the mini-PC’s chassis. GMKtec has also taken care to include rubber feet on the base to prevent slippage. Unfortunately, these feet are not built into the base, an