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NVIDIA RISC-V for NVIDIA GPUs at Hot Chips 2026
SiFive provided a comprehensive update on RISC-V standards and adoption at Hot Chips 2026, highlighting the ISA's 16-year history and its expanding role in AI compute, server processors, and security. The presentation traced RISC-V from its 2010 origins at UC Berkeley through the founding of the RISC-V Foundation to the current push into server processors with the first RVA23 silicon. SiFive emphasized that RISC-V is a global, community-developed standard, producing a larger set of processor implementations than any prior ISA, from licensable IP cores to open-source cores fitting in 125 FPGA LUTs. The talk detailed RISC-V's modular specification structure: four ratified base ISAs (RV32I, RV64I, RV32E, RV64E) with CHERI and RV128 variants in development; extensions using single-letter and Z* naming schemes; and privilege levels (user, supervisor, machine) with hypervisor and debug modes. The vector extension (RVV), ratified in 2021, supports vector-length agnostic code across datapaths from 32-bit to 2048-bit. Matrix extensions are being developed through three approaches (AME, IME, VME) plus a fast-track vector option. SiFive argued RISC-V is uniquely suited for AI across all roles—host ISA (e.g., NVIDIA CUDA port), device ISA, and self-hosted edge AI. Security features include physical memory protection, RISC-V Worlds for bus-level isolation, supervisor domains for confidential compute, and ongoing work on CHERI, speculation barriers, and memory tagging. Key to software portability are RVA profiles: RVA20 (RV64GC baseline), RVA22, and RVA23 (ratified October 2024 with mandatory vectors and hypervisor). RVA23 targets application-processor ecosystems like Android and Linux. A separate RVB23 profile serves custom software builds. SiFive also introduced optimization guidance options to align hardware and software on performance characteristics like misaligned access handling.