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CEO Interview with Yossi Meyouhas of Xsight Labs

22 d ago

Tom Jackson, a serial entrepreneur with expertise in turning around technology companies, leads SoftChip, a semiconductor startup founded by veterans from Intel and IBM. SoftChip is developing a novel logic structure called Dynamically Reconfigurable Differential Cascode Logic (DRDCL), which builds on foundational differential cascode logic invented by CTO Jim Davis, formerly of IBM’s VLSI Silicon effort. DRDCL uses a common differential cascode evaluation tree and patented Cross-Switch circuits to produce multiple useful outputs from one evaluation, enabling nanosecond-scale function switching. This yields dramatic effective-density gains: 134x for 3-high trees, 1,200x for 4-high, and 5,200x for 5-high versus fixed CMOS. Key benefits include improved performance, power, area, and thermal efficiency (PPA), as well as in-logic state retention that reduces intermediate data movement. SoftChip targets problems where fixed CMOS is costly, particularly in AI inference. Transformer decode involves repeated KV-cache movement, consuming bandwidth and power. SoftChip’s first application, Soft-NMC (near-memory compute), applies DRDCL near memory interfaces to reduce attention reduction and control traffic. Architecture models predict 60-80% reduction in repeated KV/attention movement and 3-4x sustained tokens/sec improvement in decode-dominated scenarios. The company differentiates from competitors by changing the underlying logic structure rather than improving systems above the circuit level. DRDCL does not use lookup tables or FPGA-style routing; reconfiguration occurs at the circuit level in nanoseconds. SoftChip is also working on three extensions: ARMOR, a resilience concept targeting under 1% area overhead for logic repair; Soft-TTC, for timing, throughput, and control paths with 2-5x PPA improvement; and in-logic state retention, which can yield 5-30% efficiency gains in near-memory and control blocks. Customers engage through characterized, latch-bounded DRDCL logic blocks with standard digital interfaces, allowing evaluation against CMOS equivalents and integration into standard EDA flows.