Tech news in 3 minutes

Qualcomm Investor Day 2026 Data Center Announcements CPUs, AI Accelerators, and More

26 d ago

IBM Research has announced a next-generation transistor design called Nanostack, aimed at sub-1nm geometries, specifically the 7Å (7 Angstrom) node. This development comes as the pace of Moore’s Law slows, with transistor shrinkage now occurring roughly every five years instead of every two. The Nanostack design utilizes wafer stacking—building parts of logic circuits vertically—to enable reliable manufacturing of smaller circuits and potentially extend transistor density improvements for at least a decade. The announcement provides context on current silicon lithography. Major chip fabs (TSMC, Intel, Samsung) are transitioning from FinFET to Gate All Around (GAAFET) transistors to address electron leakage at smaller nodes. GAAFET uses multiple nanosheets to surround the channel with the gate, reducing leakage. However, this technology is expected to have limited scalability, with imec projecting it will reach its limits in the early-to-mid 2030s—only five to seven years of cutting-edge use. IBM’s Nanostack aims to succeed GAAFET by stacking transistor components vertically, allowing further shrinkage beyond what planar or FinFET structures can achieve. The research team believes this approach can continue the long-standing trend of packing more transistors into chips, addressing the industry’s need for new materials and methods to sustain progress. The announcement underscores the urgency of developing successors to GAAFET as commercial production of that technology has only recently begun (e.g., Samsung SF3E, Intel 18A, TSMC N2). In summary, IBM’s Nanostack represents a potential breakthrough for sub-1nm nodes, leveraging vertical stacking to overcome the limitations of current FinFET and GAAFET designs, thereby aiming to keep Moore’s Law viable into the next decade.