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Astera Labs launches Leo 2 and Leo X CXL memory controllers, targeting data center memory economics with DDR4 reuse and PCIe Gen6/CXL 3.2 connectivity, as AI and server demand drives search for cost-effective RAM expansion. The new Leo 2 E-series and P-series smart memory controllers double memory channels from 2 to 4, supporting up to 768GB of DDR4 or 4TB of DDR5 per expander, and introduce a rare 3DPC DDR4 configuration (12 DIMMs per card). By leveraging CXL 3.2’s multi-level switching and peer-to-peer access, the controllers double bandwidth per lane via PCIe Gen6, mitigating CXL’s traditional bandwidth gap versus native DRAM. Astera emphasizes RAS capabilities—including hardware test engines and soft-ECC—to make retired DDR4 viable amid DDR5 price surges, a strategy that has gained traction since Marvell’s Structera CXL DDR4 controller became popular with hyperscalers. The Leo X-series fabric-attached controller extends memory pools directly into accelerator fabric networks for rack-scale systems, targeting AI workloads like large KV caches and in-memory databases to improve token output speeds. Astera Labs expects 2026 to be its breakout year, with Leo 2 and Leo X addressing both CPU-attached and fabric-integrated memory expansion for cost-conscious data center buildouts.