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**TSMC CoWoS-S vs CoWoS-R: Silicon Interposer for Density, RDL for Scalability in AI & HPC Chips** TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging platform offers two variants—CoWoS-S (silicon interposer) and CoWoS-R (RDL interposer)—each targeting distinct trade-offs in interconnect density, package size, and mechanical flexibility for high-performance AI accelerators and HPC systems. CoWoS-S, in production since 2012, uses a silicon interposer with through-silicon vias (TSVs) and embedded deep-trench capacitors, delivering exceptionally high wiring density and stable power delivery for demanding processors. It currently supports interposers up to ~2,700 mm² (3.3 reticle sizes), but scaling beyond this is technically difficult and expensive due to lithography and yield constraints. CoWoS-R, entering volume production in 2023, replaces silicon with a polymer-and-copper redistribution layer (RDL) interposer. This offers mechanical flexibility to absorb thermal stress, improving C4 solder joint reliability in large heterogeneous packages. CoWoS-R supports routing with a minimum pitch of 4µm (2µm lines/spaces) and enables greater scalability beyond 3.3 reticle sizes, making it attractive for extremely large AI and HPC packages with numerous chiplets or HBM memory stacks. However, CoWoS-R generally lacks the interconnect density and integrated capacitor capability of CoWoS-S. The bottom line: CoWoS-S prioritizes maximum wiring density and mature electrical performance for bandwidth-intensive computing, while CoWoS-R prioritizes large-package scalability, mechanical flexibility, and simpler manufacturing for massive multi-chip integrations. Both technologies solve different engineering challenges in modern AI and high-performance computing systems, with TSMC recommending CoWoS-R or CoWoS-L when interposer size exceeds ~3.3 reticle limits.